Abstract: According to one embodiment, there is provided pressure controlling apparatus including a detecting unit, an exhaust pipe, a regulating valve, and a pressure controlling unit. The regulating valve includes a valve port, a changing unit, and a slide valve. The valve port is communicated with the exhaust pipe. The changing unit changes a shape of the valve port to a different shape whose center is located near the central axis of the exhaust pipe. The slide valve regulates an opening degree of the valve port changed by the changing unit. The pressure controlling unit controls changing of a shape of the valve port by the changing unit and regulation of an opening degree of the valve port by the slide valve.

Abstract: According to one embodiment, a power supply control device of a plasma processing device having a plasma generation unit which generates plasma in a process chamber. The power supply control device includes a radio frequency power supply, a storage unit, and a matching circuit. The radio frequency power supply supplies a power to the plasma generation unit. The storage unit stores matching information including a first matching value, a second process condition, and a third matching value. The first matching value corresponds to process information of a first process condition. The second matching value corresponds to process information of a second process condition. The third matching value corresponds to process information of a transient state where the first process condition is being switched to the second process condition. The matching circuit matches impedances based on the matching information.

Abstract: According to one embodiment, a flow rate adjusting unit is disposed on a gas passageway and includes a valve that adjusts the flow rate of a gas and an actuator that controls the displacement amount of the valve. A displacement amount storage unit stores displacement amount information in which a displacement amount of the valve, used when a gas flows into the gas passageway at a flow rate defined according to a process procedure before performing the process procedure, is obtained in advance for each process procedure. A setting circuit acquires the displacement amount corresponding to the process procedure from the displacement amount storage unit, and controls the actuator on the basis of the acquired displacement amount.

Abstract: According to one embodiment, there is provided a coaxial cable that transmits radio frequency power. The coaxial cable includes an inner tube, an outer tube, and an insulating support member. The inner tube is made of a conductor. The outer tube is disposed outside the inner tube coaxially with the inner tube and is made of a conductor. The insulating support member is disposed between the inner tube and the outer tube. Cooling gas flows into at least one of a first space inside the inner tube and a second space between the inner tube and the outer tube.

Abstract: According to one embodiment, there is provided pressure controlling apparatus including a detecting unit, an exhaust pipe, a regulating valve, and a pressure controlling unit. The regulating valve includes a valve port, a changing unit, and a slide valve. The valve port is communicated with the exhaust pipe. The changing unit changes a shape of the valve port to a different shape whose center is located near the central axis of the exhaust pipe. The slide valve regulates an opening degree of the valve port changed by the changing unit. The pressure controlling unit controls changing of a shape of the valve port by the changing unit and regulation of an opening degree of the valve port by the slide valve.

Abstract: According to one embodiment, a power supply control device of a plasma processing device having a plasma generation unit which generates plasma in a process chamber. The power supply control device includes a radio frequency power supply, a storage unit, and a matching circuit. The radio frequency power supply supplies a power to the plasma generation unit. The storage unit stores matching information including a first matching value, a second process condition, and a third matching value. The first matching value corresponds to process information of a first process condition. The second matching value corresponds to process information of a second process condition. The third matching value corresponds to process information of a transient state where the first process condition is being switched to the second process condition. The matching circuit matches impedances based on the matching information.

Abstract: According to one embodiment, a flow rate adjusting unit is disposed on a gas passageway and includes a valve that adjusts the flow rate of a gas and an actuator that controls the displacement amount of the valve. A displacement amount storage unit stores displacement amount information in which a displacement amount of the valve, used when a gas flows into the gas passageway at a flow rate defined according to a process procedure before performing the process procedure, is obtained in advance for each process procedure. A setting circuit acquires the displacement amount corresponding to the process procedure from the displacement amount storage unit, and controls the actuator on the basis of the acquired displacement amount.

Abstract: According to one embodiment, there is provided a plasma treatment apparatus including an electrode, a first power supply circuit, a plasma generating unit, a second power supply circuit, a sensing unit, and a control unit. The electrode is arranged inside a treatment chamber. On the electrode, a substrate to be treated is placed. The first power supply circuit supplies power to the electrode. The plasma generating unit generates plasma in a space separated from the electrode inside the treatment chamber. The second power supply circuit supplies power to the plasma generating unit. The sensing unit senses a parameter output from the first power supply circuit. The control unit controls power supplied from the second power supply circuit so that the parameter sensed by the sensing unit becomes close to or substantially equal to a target value.

Abstract: A semiconductor device according to an embodiment of the present invention includes: a square pole-shaped channel portion made from a first semiconductor layer formed on a substrate, and surrounded with four side faces; a gate electrode formed on a first side face of the channel portion, and a second side face of the channel portion opposite to the first side face through respective gate insulating films; a source region having a conductivity type different from that of the channel portion and being formed on a third side face of the channel portion, the source region including a second semiconductor layer having a lattice constant different from that of the first semiconductor layer and being formed directly on the substrate; and a drain region having a conductivity type different from that of the channel portion and being formed on a fourth side face of the channel portion opposite to the third side face, the drain region including the second semiconductor layer being formed directly on the substrate.

Abstract: A semiconductor device includes at least two adjacent memory cell blocks, each of the memory cell blocks having a plurality of memory cell units, each of memory cell units having a plurality of electrically reprogrammable and erasable memory cells connected in series, a plurality of cell gates for selecting the plurality of memory cells within the two adjacent memory cell blocks, each of the plurality of cell gates being formed with roughly rectangular closed loops or roughly U shaped open loops, each of the loops being connected to a corresponding cell of the memory cells in a corresponding memory cell unit of the plurality of memory cell units within one of the two adjacent memory cell blocks and being connected to a corresponding memory cell of the memory cells in a corresponding memory cell unit of the plurality of memory cell units within the other memory cell block of the two adjacent memory cell blocks and a plurality of pairs of first and second selection gates for selecting the memory cell block, the

Abstract: A semiconductor device includes at least two adjacent memory cell blocks, each of the memory cell blocks having a plurality of memory cell units, each of memory cell units having a plurality of electrically reprogrammable and erasable memory cells connected in series, a plurality of cell gates for selecting the plurality of memory cells within the two adjacent memory cell blocks, each of the plurality of cell gates being formed with roughly rectangular closed loops or roughly U shaped open loops, each of the loops being connected to a corresponding cell of the memory cells in a corresponding memory cell unit of the plurality of memory cell units within one of the two adjacent memory cell blocks and being connected to a corresponding memory cell of the memory cells in a corresponding memory cell unit of the plurality of memory cell units within the other memory cell block of the two adjacent memory cell blocks and a plurality of pairs of first and second selection gates for selecting the memory cell block, the

Abstract: A semiconductor device includes at least two adjacent memory cell blocks, each of the memory cell blocks having a plurality of memory cell units, each of memory cell units having a plurality of electrically reprogrammable and erasable memory cells connected in series, a plurality of cell gates for selecting the plurality of memory cells within the two adjacent memory cell blocks, each of the plurality of cell gates being formed with roughly rectangular closed loops or roughly U shaped open loops, each of the loops being connected to a corresponding cell of the memory cells in a corresponding memory cell unit of the plurality of memory cell units within one of the two adjacent memory cell blocks and being connected to a corresponding memory cell of the memory cells in a corresponding memory cell unit of the plurality of memory cell units within the other memory cell block of the two adjacent memory cell blocks and a plurality of pairs of first and second selection gates for selecting the memory cell block, the

Abstract: A method of manufacturing a semiconductor device, includes forming a sacrifice film on an etching target film, forming an etching mask on the sacrifice film, etching the etching target film using the etching mask as a mask, removing the sacrifice film to allow the etching mask to adhere to the etching target film, and removing the etching mask.

Abstract: A semiconductor device according to an embodiment of the present invention includes: a square pole-shaped channel portion made from a first semiconductor layer formed on a substrate, and surrounded with four side faces; a gate electrode formed on a first side face of the channel portion, and a second side face of the channel portion opposite to the first side face through respective gate insulating films; a source region having a conductivity type different from that of the channel portion and being formed on a third side face of the channel portion, the source region including a second semiconductor layer having a lattice constant different from that of the first semiconductor layer and being formed directly on the substrate; and a drain region having a conductivity type different from that of the channel portion and being formed on a fourth side face of the channel portion opposite to the third side face, the drain region including the second semiconductor layer being formed directly on the substrate.

Abstract: A semiconductor device includes at least two adjacent memory cell blocks, each of the memory cell blocks having a plurality of memory cell units, each of memory cell units having a plurality of electrically reprogrammable and erasable memory cells connected in series, a plurality of cell gates for selecting the plurality of memory cells within the two adjacent memory cell blocks, each of the plurality of cell gates being formed with roughly rectangular closed loops or roughly U shaped open loops, each of the loops being connected to a corresponding cell of the memory cells in a corresponding memory cell unit of the plurality of memory cell units within one of the two adjacent memory cell blocks and being connected to a corresponding memory cell of the memory cells in a corresponding memory cell unit of the plurality of memory cell units within the other memory cell block of the two adjacent memory cell blocks and a plurality of pairs of first and second selection gates for selecting the memory cell block, the

Abstract: A semiconductor device according to an embodiment of the present invention includes: a square pole-shaped channel portion made from a first semiconductor layer formed on a substrate, and surrounded with four side faces; a gate electrode formed on a first side face of the channel portion, and a second side face of the channel portion opposite to the first side face through respective gate insulating films; a source region having a conductivity type different from that of the channel portion and being formed on a third side face of the channel portion, the source region including a second semiconductor layer having a lattice constant different from that of the first semiconductor layer and being formed directly on the substrate; and a drain region having a conductivity type different from that of the channel portion and being formed on a fourth side face of the channel portion opposite to the third side face, the drain region including the second semiconductor layer being formed directly on the substrate.

Abstract: A semiconductor device includes at least two adjacent memory cell blocks, each of the memory cell blocks having a plurality of memory cell units, each of memory cell units having a plurality of electrically reprogrammable and erasable memory cells connected in series, a plurality of cell gates for selecting the plurality of memory cells within the two adjacent memory cell blocks, each of the plurality of cell gates being formed with roughly rectangular closed loops or roughly U shaped open loops, each of the loops being connected to a corresponding cell of the memory cells in a corresponding memory cell unit of the plurality of memory cell units within one of the two adjacent memory cell blocks and being connected to a corresponding memory cell of the memory cells in a corresponding memory cell unit of the plurality of memory cell units within the other memory cell block of the two adjacent memory cell blocks and a plurality of pairs of first and second selection gates for selecting the memory cell block, the

Abstract: A semiconductor device includes at least two adjacent memory cell blocks, each of the memory cell blocks having a plurality of memory cell units, each of memory cell units having a plurality of electrically reprogrammable and erasable memory cells connected in series, a plurality of cell gates for selecting the plurality of memory cells within the two adjacent memory cell blocks, each of the plurality of cell gates being formed with roughly rectangular closed loops or roughly U shaped open loops, each of the loops being connected to a corresponding cell of the memory cells in a corresponding memory cell unit of the plurality of memory cell units within one of the two adjacent memory cell blocks and being connected to a corresponding memory cell of the memory cells in a corresponding memory cell unit of the plurality of memory cell units within the other memory cell block of the two adjacent memory cell blocks and a plurality of pairs of first and second selection gates for selecting the memory cell block, the

Abstract: A semiconductor device according to an embodiment of the present invention includes: a square pole-shaped channel portion made from a first semiconductor layer formed on a substrate, and surrounded with four side faces; a gate electrode formed on a first side face of the channel portion, and a second side face of the channel portion opposite to the first side face through respective gate insulating films; a source region having a conductivity type different from that of the channel portion and being formed on a third side face of the channel portion, the source region including a second semiconductor layer having a lattice constant different from that of the first semiconductor layer and being formed directly on the substrate; and a drain region having a conductivity type different from that of the channel portion and being formed on a fourth side face of the channel portion opposite to the third side face, the drain region including the second semiconductor layer being formed directly on the substrate.

Abstract: A method of manufacturing a semiconductor device, includes forming a sacrifice film on an etching target film, forming an etching mask on the sacrifice film, etching the etching target film using the etching mask as a mask, removing the sacrifice film to allow the etching mask to adhere to the etching target film, and removing the etching mask.