Abstract: In the memory cell matrix of a semiconductor integrated circuit device having a non-volatile semiconductor memory cell portion and a logic portion, a second-layered Al wires are formed on the first-layered Al wires, with an interlayer insulating film interposed therebetween. The pattern of the second-layered Al wires is the same as that of the first-layered Al wires. This structure reduces the labor for designing mask data, and increases the coating ratio of a resist to an Al layer while minimizing a reduction in the transmittance of ultraviolet ray. As a result, the amount of a reaction compound supplied from the resist into the Al layer for forming the second-layered Al wires increases, which prevents the second-layered Al wires from being undercut. Thus, the second and subsequent-layered Al wires of the logic portion can be effectively prevented from being thinned.

Abstract: In a method of fabricating a semiconductor device in which at least one of a first conductive layer (polysilicon film) and a second conductive layer (polysilicon film) on a semiconductor substrate is used as a gate electrode of a MOS transistor to be formed on the semiconductor substrate, channel ion implantation for controlling the threshold voltages of the MOS transistors is performed by using the first conductive layer (polysilicon film) as a buffer film. Since the first conductive layer used as the gate electrode is also used as the buffer film, a dummy gate oxide film need not be provided, which is used as a buffer film for the channel ion implantation. Removal of the dummy gate oxide film is also unnecessary. Thus, it is possible to reduce the number of times of a dilute HF treatment which is performed to remove a dummy gate oxide film. The result is that a decrease in thickness of the field oxide film is reduced.

Abstract: A manufacturing method of a semiconductor memory device includes the steps of selectively forming a field oxide film and a gate oxide film on a semiconductor substrate, depositing a first conductive layer on an entire surface of the resultant structure, selectively etching the first conductive layer located in a region other than an element region, depositing a second conductive layer on an entire surface of the resultant structure, and etching the first conductive layer and the second conductive layer using the same mask to form a plurality of floating gates by the first conductive layer and to form a plurality of control gates by the second conductive layer, wherein the step of selectively etching the first conductive layer includes the first etching step of forming cell slits for separating the plurality of floating gates from each other and the second etching step of forming removed regions each of which includes only one end of each of the plurality of control gates.