Abstract: A semiconductor chip (2,3) is mounted on the heat spreader (1). A frame (4) is bonded to an upper surface of the semiconductor chip (2,3). Mold resin (9) seals the heat spreader (1), the semiconductor chip (2,3) and the frame (4) and has a recess (10) provided on an upper surface of the mold resin (9). A heat dissipation plate (12) is externally attached to the recess (10) via a thermally conductive material (11) having thermal conductivity higher than that of the mold resin (9). The heat dissipation plate (12) is insulated from the semiconductor chip (2,3) and the frame (4) by the mold resin (9). The heat dissipation plate (12) is a flat plate having an upper surface and a lower surface which are opposite to each other and flat.

Abstract: An object of the present invention is to provide a semiconductor device in which the effect of dimensional tolerance can be reduced, and a method for manufacturing the same. The semiconductor device according to the present invention includes: a plurality of cooling plates each having a coolant passage inside; spacers disposed to stack the cooling plates with spaces; at least one semiconductor package disposed on at least one principal surface of at least one of the cooling plates; and a spring plate disposed between adjacent ones of the cooling plates, the spring plate biasing the at least one semiconductor package toward the cooling plates.

Abstract: An object is to provide a technique capable of suppressing generation of a crack in a molding resin and suppressing entry of moisture from the outside. A semiconductor device includes a heat spreader, a semiconductor element provided on an upper surface of the heat spreader, an insulating sheet provided on a lower surface of the heat spreader, a lead frame joined to an upper surface of the semiconductor element via solder, and a molding resin that seals one end side of the lead frame, the semiconductor element, the heat spreader, and the insulating sheet. A hole is formed from an upper surface of the molding resin to a joining surface of the lead frame with the semiconductor element, and the hole is filled with a low Young's modulus resin having a Young's modulus lower than that of the molding resin.

Abstract: It is an object to provide technology enabling suppression of contact deformation of pin fins during assembly of a semiconductor device and the like. A semiconductor device includes a base plate, a semiconductor element, and a resin member. The base plate has a plurality of pin fins on a lower surface thereof. The semiconductor element is mounted on an upper side of the base plate. The resin member covers at least a side surface of the semiconductor element. The resin member has a rib covering a side surface of the base plate, and a lower end of the rib is located below lower ends of the plurality of pin fins.

Abstract: A semiconductor device includes a semiconductor element having an electrode, material of which is first metal, a lead frame through which a plurality of holes extend with an outer contour of the electrode being avoided in a first portion, and having the first portion, material of which is second metal, a bonding layer interposed between the first portion and the electrode, and solder being inside the plurality of holes and adjoining the bonding layer, the solder being thicker than the bonding layer. The plurality of holes have a plurality of first holes extending through the first portion in a thickness direction of the first portion. The bonding layer has a first bonding layer located on the electrode side and being an alloy of the first metal and tin, and a second bonding layer located on the first portion side and being an alloy of the second metal and tin. The plurality of first holes are located in an annular region inside the outer contour of the electrode.

Abstract: A semiconductor device according to the present disclosure includes a semiconductor substrate, a first electrode provided on the semiconductor substrate, an insulating layer including a first part provided on an upper surface of the first electrode, a second electrode including a main portion and an eaves portion, the main portion being provided on the upper surface of the first electrode, the eaves portion extending over the first part and solder covering an upper surface of the main portion and a part of an upper surface of the eaves portion wherein the insulating layer includes a second part covering a part of the upper surface of the eaves portion, the part being closer to an end portion of the eaves portion than the part covered by the solder and a third part connecting the first part and the second part and covering the end portion of the eaves portion.

Abstract: A semiconductor device includes a semiconductor element having an electrode, material of which is first metal, a lead frame through which a plurality of holes extend with an outer contour of the electrode being avoided in a first portion, and having the first portion, material of which is second metal, a bonding layer interposed between the first portion and the electrode, and solder being inside the plurality of holes and adjoining the bonding layer, the solder being thicker than the bonding layer. The plurality of holes have a plurality of first holes extending through the first portion in a thickness direction of the first portion. The bonding layer has a first bonding layer located on the electrode side and being an alloy of the first metal and tin, and a second bonding layer located on the first portion side and being an alloy of the second metal and tin. The plurality of first holes are located in an annular region inside the outer contour of the electrode.

Abstract: An object is to provide a technique for reducing process steps, and a stress generated at the peripheral portion of the joint portion between an electrode of a semiconductor element and a lead frame. A semiconductor device includes the following: a semiconductor element disposed on a heat spreader; a lead frame joined to an emitter electrode of the semiconductor element via solder, which is a joining material; a metal film disposed on a surface of the emitter electrode; and an anti-oxidation film disposed on a surface of the metal film. The metal film has a peripheral portion that is entirely exposed from the anti-oxidation film.

Abstract: An object of the present invention is to provide a semiconductor device in which the effect of dimensional tolerance can be reduced, and a method for manufacturing the same. The semiconductor device according to the present invention includes: a plurality of cooling plates each having a coolant passage inside; spacers disposed to stack the cooling plates with spaces; at least one semiconductor package disposed on at least one principal surface of at least one of the cooling plates; and a spring plate disposed between adjacent ones of the cooling plates, the spring plate biasing the at least one semiconductor package toward the cooling plates.

Abstract: An object is to provide a technique for reducing process steps, and a stress generated at the peripheral portion of the joint portion between an electrode of a semiconductor element and a lead frame. A semiconductor device includes the following: a semiconductor element disposed on a heat spreader; a lead frame joined to an emitter electrode of the semiconductor element via solder, which is a joining material; a metal film disposed on a surface of the emitter electrode; and an anti-oxidation film disposed on a surface of the metal film. The metal film has a peripheral portion that is entirely exposed from the anti-oxidation film.

Abstract: A semiconductor device according to the present invention includes a ceramic substrate, a plurality of circuit patterns arranged on a surface of the ceramic substrate, a semiconductor element arranged on an upper surface of at least one circuit pattern, and a sealing resin for sealing the ceramic substrate, the plurality of circuit patterns, and the semiconductor element, in which an undercut part is formed in opposed side surfaces of the circuit patterns adjacent to one another, the undercut part is configured such that an end of an upper surface of the circuit pattern protrudes outside the circuit pattern more than an end of a lower surface of the circuit pattern on the ceramic substrate, and the undercut part is also filled with the sealing resin.

Abstract: A semiconductor device according to the present invention includes a ceramic substrate, a plurality of circuit patterns arranged on a surface of the ceramic substrate, a semiconductor element arranged on an upper surface of at least one circuit pattern, and a sealing resin for sealing the ceramic substrate, the plurality of circuit patterns, and the semiconductor element, in which an undercut part is formed in opposed side surfaces of the circuit patterns adjacent to one another, the undercut part is configured such that an end of an upper surface of the circuit pattern protrudes outside the circuit pattern more than an end of a lower surface of the circuit pattern on the ceramic substrate, and the undercut part is also filled with the sealing resin.

Abstract: A power module includes a first substrate with a power semiconductor device mounted thereon, a second substrate with a control circuit for controlling the power semiconductor device formed thereon, a smoothing capacitor electrically connected to the power semiconductor device for smoothing a voltage to be externally supplied to the power semiconductor device, and a case including a case frame and a case lid. The case has an interior in which the first substrate, the second substrate and the smoothing capacitor are disposed, and the smoothing capacitor is disposed in contact with a side surface of the case frame.

Abstract: A power module includes a box-shaped smoothing capacitor (20) for smoothing a DC supply voltage to be externally applied to a power semiconductor device (5). The smoothing capacitor (20) is in contact with a side surface of a case frame (6) including a side (along which an N-terminal (8N) and a P-terminal (8P) are arranged) of a top surface of the case frame (6), and has a top surface level with the top surface of the case frame (6). An N-electrode (21N) and a P-electrode (21P) of the smoothing capacitor (20) are disposed on the top surface of the smoothing capacitor (20) and in proximity to the N-terminal (8N) and the P-terminal (8P) of a power module body portion (99), respectively. The power module can reduce a circuit inductance, is reduced in size and weight, and has good resistance to vibration.

Abstract: A power module includes a substrate with a power semiconductor device mounted thereon, a case having an interior in which the substrate is disposed, a cooling fin having a surface on which the substrate and the case are placed, and a smoothing capacitor disposed on an opposite surface of the cooling fin from the surface on which the substrate is placed, the smoothing capacitor being electrically connected to the power semiconductor device for smoothing a voltage to be externally supplied to the power semiconductor device.

Abstract: A semiconductor device for controlling electricity including a metal base plate and at least one insulating substrate. The insulating substrate includes an insulator plate, a back-side pattern on a back face of the insulator plate and bonded to the metal base plate, and two circuit patterns located on a front face of the insulator plate and above the back-side pattern. Each of the two circuit patterns has an “L” shape and extends along two sides of the insulator plate that are continued and perpendicular to each other. The two circuit patterns are also arranged at opposed corners of the insulator plate in a centrosymmetrical relation each other. Further, in each circuit pattern, a switching element is sandwiched between a free-wheel diode and an electrode area.

Abstract: A power module includes a box-shaped smoothing capacitor (20) for smoothing a DC supply voltage to be externally applied to a power semiconductor device (5). The smoothing capacitor (20) is in contact with a side surface of a case frame (6) including a side (along which an N-terminal (8N) and a P-terminal (8P) are arranged) of a top surface of the case frame (6), and has a top surface level with the top surface of the case frame (6). An N-electrode (21N) and a P-electrode (21P) of the smoothing capacitor (20) are disposed on the top surface of the smoothing capacitor (20) and in proximity to the N-terminal (8N) and the P-terminal (8P) of a power module body portion (99), respectively. The power module can reduce a circuit inductance, is reduced in size and weight, and has good resistance to vibration.

Abstract: A power module includes a box-shaped smoothing capacitor (20) for smoothing a DC supply voltage to be externally applied to a power semiconductor device (5). The smoothing capacitor (20) is in contact with a side surface of a case frame (6) including a side (along which an N-terminal (8N) and a P-terminal (8P) are arranged) of a top surface of the case frame (6), and has a top surface level with the top surface of the case frame (6). An N-electrode (21N) and a P-electrode (21P) of the smoothing capacitor (20) are disposed on the top surface of the smoothing capacitor (20) and in proximity to the N-terminal (8N) and the P-terminal (8P) of a power module body portion (99), respectively. The power module can reduce a circuit inductance, is reduced in size and weight, and has good resistance to vibration.

Abstract: It is an object to provide a power semiconductor device having a circuit pattern and a lower pattern made of an Al alloy for cost reduction and enabling reduction in heat resistance and improvement in resistance of a soldering layer to heat cycle. A substrate of semiconductor elements is mounted on a metal base plate made of a Cu alloy. The substrate of semiconductor elements includes an insulating substrate made of ceramics or the like. The circuit pattern and the lower pattern both made of an Al alloy are formed on an upper surface and a lower surface of the insulating substrate. The lower pattern is provided on an entire surface of the insulating substrate and joined onto the metal base plate through the soldering layer. Thicknesses of the metal base plate and the insulating substrate are respectively set to be 3.5 to 5.5 mm and 0.5 to 1 mm, for example. A thickness of the circuit pattern is set to be 0.4 to 0.6 mm and thicknesses of the lower pattern and the soldering layer are respectively set to be 0.

Abstract: A semiconductor device for controlling electricity includes: