Patents by Inventor Nobuyoshi Matsuura
Nobuyoshi Matsuura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9153686Abstract: In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.Type: GrantFiled: July 24, 2014Date of Patent: October 6, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Masaki Shiraishi, Tomoaki Uno, Nobuyoshi Matsuura
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Patent number: 9099550Abstract: A semiconductor device has a MOSFET and a Schottky barrier diode. A source electrode of the MOSFET is disposed over a main surface of the semiconductor substrate and is coupled to a source region in a well region of the semiconductor substrate. The Schottky barrier diode is adjacent to the MOSFET and includes a part of the source electrode and a part of the main surface of the semiconductor substrate.Type: GrantFiled: October 30, 2014Date of Patent: August 4, 2015Assignee: Renesas Electronics CorporationInventors: Nobuyuki Shirai, Nobuyoshi Matsuura, Yoshito Nakazawa
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Publication number: 20150194894Abstract: A trench MOSFET is disclosed that includes a semiconductor substrate having a vertically oriented trench containing a gate. The trench MOSFET further includes a source, a drain, and a conductive element. The conductive element, like the gate is contained in the trench, and extends between the gate and a bottom of the trench. The conductive element is electrically isolated from the source, the gate, and the drain. When employed in a device such as a DC-DC converter, the trench MOSFET may reduce power losses and electrical and electromagnetic noise.Type: ApplicationFiled: March 24, 2015Publication date: July 9, 2015Inventors: Tetsuo Sato, Tomoaki Uno, Hirokazu Kato, Nobuyoshi Matsuura
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Patent number: 9000497Abstract: A trench MOSFET is disclosed that includes a semiconductor substrate having a vertically oriented trench containing a gate. The trench MOSFET further includes a source, a drain, and a conductive element. The conductive element, like the gate is contained in the trench, and extends between the gate and a bottom of the trench. The conductive element is electrically isolated from the source, the gate, and the drain. When employed in a device such as a DC-DC converter, the trench MOSFET may reduce power losses and electrical and electromagnetic noise.Type: GrantFiled: September 14, 2012Date of Patent: April 7, 2015Assignee: Renesas Electronics CorporationInventors: Tetsuo Sato, Tomoaki Uno, Hirokazu Kato, Nobuyoshi Matsuura
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Publication number: 20150054069Abstract: A semiconductor device for use in a power supply circuit has first and second MOSFETS. The source-drain path of one of the MOSFETS are coupled to the source-drain path of the other, and a load element is coupled to a connection node of the source-drain paths. The second MOSFET is formed on a semiconductor substrate with a Schottky barrier diode. First gate electrodes of the second MOSFET are formed in trenches in a first region of the semiconductor substrate, while second gate electrodes of the second MOSFET are formed in trenches in a second region of the semiconductor substrate. The first and second gate electrodes are electrically connected together. Portions of the Schottky barrier diode are formed between adjacent ones of the second gate electrodes. A center-to-center spacing between adjacent first gate electrodes is smaller than a center-to-center spacing between adjacent second gate electrodes.Type: ApplicationFiled: October 30, 2014Publication date: February 26, 2015Inventors: Nobuyuki SHIRAI, Nobuyoshi MATSUURA, Yoshito NAKAZAWA
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Publication number: 20150028400Abstract: A semiconductor device includes a gate electrode GE electrically connected to a gate portion which is made of a polysilicon film provided in the inside of a plurality of grooves formed in a striped form along the direction of T of a chip region CA wherein the gate electrode GE is formed as a film at the same layer level as a source electrode SE electrically connected to a source region formed between adjacent stripe-shaped grooves and the gate electrode GE is constituted of a gate electrode portion G1 formed along a periphery of the chip region CA and a gate finger portion G2 arranged so that the chip region CA is divided into halves along the direction of X. The source electrode SE is constituted of an upper portion and a lower portion, both relative to the gate finger portion G2, and the gate electrode GE and the source electrode SE are connected to a lead frame via a bump electrode.Type: ApplicationFiled: October 14, 2014Publication date: January 29, 2015Inventors: Nobuyuki Shirai, Nobuyoshi Matsuura
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Patent number: 8928071Abstract: A semiconductor device has a semiconductor substrate with a plurality of transistor cell regions. Each transistor cell region includes a plurality of trenches disposed in the semiconductor substrate, a well region between the plurality of trenches, and a source region of a MOSFET in the well region. A source electrode of the MOSFET is in contact with a top surface of the source region in each of the plurality of transistor cell regions. The source electrode is in contact with a part of a main surface of the semiconductor substrate so as to form a Schottky junction in a Schottky cell region disposed between the plurality of transistor cell regions. The Schottky junction is lower than a portion of the main surface between the Schottky junction and one of the transistor cell regions.Type: GrantFiled: March 16, 2013Date of Patent: January 6, 2015Assignee: Renesas Electronics CorporationInventors: Nobuyuki Shirai, Nobuyoshi Matsuura, Yoshito Nakazawa
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Patent number: 8901838Abstract: The semiconductor device is included in the LED driving circuit (current regulator) of driving the LED array (with series-connected number m×parallel-connected number n), and is formed of a plurality (n pieces) of LED driving devices of controlling a current (constant-current driving) flowing in each string. A vertical semiconductor device, for example, a vertical MOSFET is used as the LED driving device. Both of a main device functioning as a constant-current driving device and a subsidiary device functioning as a circuit-breaking switch during dimming are formed inside a chip of the device, which are formed of the vertical semiconductor devices. In a first surface of the device, each source region of the main device and the subsidiary device is formed so as to be insulated from each other through an isolation region.Type: GrantFiled: July 27, 2012Date of Patent: December 2, 2014Assignee: Renesas Electronics CorporationInventors: Noboru Akiyama, Takayuki Hashimoto, Takashi Hirao, Nobuyoshi Matsuura, Hideo Ishii
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Publication number: 20140332878Abstract: In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.Type: ApplicationFiled: July 24, 2014Publication date: November 13, 2014Inventors: Masaki SHIRAISHI, Tomoaki UNO, Nobuyoshi MATSUURA
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Patent number: 8884361Abstract: A semiconductor device which includes a gate electrode electrically connected to a gate portion made of a polysilicon film provided inside of a plurality of grooves formed in a striped form along a direction of a chip region. The gate electrode is formed as a film at the same layer level as a source electrode electrically connected to a source region formed between adjacent stripe-shaped grooves. The gate electrode is constituted of a gate electrode portion formed along a periphery of the chip region and a gate finger portion arranged to divide the chip region into halves. The source electrode is constituted of an upper portion and a lower portion relative to the gate finger portion, and the gate electrode and the source electrode are connected to a lead frame via a bump electrode.Type: GrantFiled: January 13, 2012Date of Patent: November 11, 2014Assignee: Renesas Electronics CorporationInventors: Nobuyuki Shirai, Nobuyoshi Matsuura
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Publication number: 20140312510Abstract: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.Type: ApplicationFiled: July 2, 2014Publication date: October 23, 2014Inventors: Yukihiro SATOU, Tomoaki UNO, Nobuyoshi MATSUURA, Masaki SHIRAISHI
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Patent number: 8853846Abstract: In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.Type: GrantFiled: November 5, 2013Date of Patent: October 7, 2014Assignee: Renesas Electronics CorporationInventors: Masaki Shiraishi, Tomoaki Uno, Nobuyoshi Matsuura
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Patent number: 8796827Abstract: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.Type: GrantFiled: August 29, 2013Date of Patent: August 5, 2014Assignee: Renesas Electronics CorporationInventors: Yukihiro Satou, Tomoaki Uno, Nobuyoshi Matsuura, Masaki Shiraishi
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Publication number: 20140077778Abstract: A trench MOSFET is disclosed that includes a semiconductor substrate having a vertically oriented trench containing a gate. The trench MOSFET further includes a source, a drain, and a conductive element. The conductive element, like the gate is contained in the trench, and extends between the gate and a bottom of the trench. The conductive element is electrically isolated from the source, the gate, and the drain. When employed in a device such as a DC-DC converter, the trench MOSFET may reduce power losses and electrical and electromagnetic noise.Type: ApplicationFiled: September 14, 2012Publication date: March 20, 2014Inventors: Tetsuo Sato, Tomoaki Uno, Hirokazu Kato, Nobuyoshi Matsuura
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Publication number: 20140054692Abstract: In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.Type: ApplicationFiled: November 5, 2013Publication date: February 27, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Masaki SHIRAISHI, Tomoaki UNO, Nobuyoshi MATSUURA
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Publication number: 20140003002Abstract: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.Type: ApplicationFiled: August 29, 2013Publication date: January 2, 2014Applicant: Renesas Electronics CorporationInventors: Yukihiro SATOU, Tomoaki UNO, Nobuyoshi MATSUURA, Masaki SHIRAISHI
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Patent number: 8592914Abstract: The electrical characteristics of a semiconductor device are enhanced. In the package of the semiconductor device, there are encapsulated first and second semiconductor chips with a power MOS-FET formed therein and a third semiconductor chip with a control circuit for controlling their operation formed therein. The bonding pads for source electrode of the first semiconductor chip on the high side are electrically connected to a die pad through a metal plate. The bonding pad for source electrode of the second semiconductor chip on the low side is electrically connected to lead wiring through a metal plate. The metal plate includes a first portion in contact with the bonding pad of the second semiconductor chip, a second portion extended from a short side of the first portion to the lead wiring, and a third portion extended from a long side of the first portion to the lead wiring.Type: GrantFiled: July 11, 2012Date of Patent: November 26, 2013Assignee: Renesas Electronics CorporationInventors: Tomoaki Uno, Nobuyoshi Matsuura, Yukihiro Sato, Keiichi Okawa, Tetsuya Kawashima, Kisho Ashida
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Patent number: 8592904Abstract: In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.Type: GrantFiled: August 17, 2012Date of Patent: November 26, 2013Assignee: Renesas Electronics CorporationInventors: Masaki Shiraishi, Tomoaki Uno, Nobuyoshi Matsuura
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Patent number: 8575733Abstract: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.Type: GrantFiled: December 17, 2012Date of Patent: November 5, 2013Assignee: Renesas Electronics CorporationInventors: Yohihiro Satou, Tomoaki Uno, Nobuyoshi Matsuura, Masaki Shiraishi
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Patent number: 8536643Abstract: A semiconductor device includes a gate electrode GE electrically connected to a gate portion which is made of a polysilicon film provided in the inside of a plurality of grooves formed in a striped form along the direction of T of a chip region CA wherein the gate electrode GE is formed as a film at the same layer level as a source electrode SE electrically connected to a source region formed between adjacent stripe-shaped grooves and the gate electrode GE is constituted of a gate electrode portion G1 formed along a periphery of the chip region CA and a gate finger portion G2 arranged so that the chip region CA is divided into halves along the direction of X. The source electrode SE is constituted of an upper portion and a lower portion, both relative to the gate finger portion G2, and the gate electrode GE and the source electrode SE are connected to a lead frame via a bump electrode.Type: GrantFiled: February 19, 2010Date of Patent: September 17, 2013Assignee: Renesas Electronics CorporationInventors: Nobuyuki Shirai, Nobuyoshi Matsuura