Patents by Inventor Nobuyoshi Nakaya

Nobuyoshi Nakaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and operation monitoring method for semiconductor device
    Patent number: 8742786
    Abstract: A semiconductor device includes a monitor including a first element coupled between a first power supply line and a second power supply line, and a load for increasing a load value between the first element and the first power supply line or the second power supply line, and a determination unit which determines an operating state of the first element based on an output of the monitor.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: June 3, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kazufumi Komura, Katsumi Furukawa, Keiichi Fujimura, Takayoshi Nakamura, Tohru Yasuda, Hirohisa Nishiyama, Nobuyoshi Nakaya, Kanta Yamamoto, Shigetaka Asano
  • SEMICONDUCTOR DEVICE AND OPERATION MONITORING METHOD FOR SEMICONDUCTOR DEVICE
    Publication number: 20090243627
    Abstract: A semiconductor device includes a monitor including a first element coupled between a first power supply line and a second power supply line, and a load for increasing a load value between the first element and the first power supply line or the second power supply line, and a determination unit which determines an operating state of the first element based on an output of the monitor.
    Type: Application
    Filed: March 24, 2009
    Publication date: October 1, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Kazufumi KOMURA, Katsumi Furukawa, Keiichi Fujimura, Takayoshi Nakamura, Tohru Yasuda, Hirohisa Nishiyama, Nobuyoshi Nakaya, Kanta Yamamoto, Shigetaka Asano
  • Semiconductor memory, data read method for semiconductor memory and data storage apparatus
    Patent number: 6061278
    Abstract: A semiconductor memory device comprises a plurality of memory cells for storing cell data. Word lines are connected to the memory cells. A first bit line includes a primary bit line connected to each memory cell and a secondary bit line. A first switching circuit is connected between the primary and secondary bit lines. A sense amplifier is connected to the secondary bit line. A second bit line is connected to the sense amplifier. A second switching circuit is connected between the second bit line and one of the primary and secondary bit lines.
    Type: Grant
    Filed: October 5, 1998
    Date of Patent: May 9, 2000
    Assignee: Fujitsu Limited
    Inventors: Yoshiharu Kato, Nobuyoshi Nakaya