Patents by Inventor Nobuyoshi Takeuchi

Nobuyoshi Takeuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5907183
    Abstract: A tunnel oxide film is formed on the surface of a p-type silicon substrate, and a floating gate electrode made from a polysilicon film is formed on the surface of the tunnel oxide film. On the surface of the floating gate electrode, a control gate electrode is formed via an NON film formed by sequentially stacking a silicon nitride film, a silicon oxide film, and a silicon nitride film. A side oxide film is formed on the side surfaces of the floating gate electrode and the control gate electrode. Source and drain regions made from an n-type diffused layer are formed on the surfaces of element regions of the silicon substrate on the two sides of the floating gate electrodes.
    Type: Grant
    Filed: May 12, 1997
    Date of Patent: May 25, 1999
    Assignees: NKK Corporation, Macronix International Co., Ltd.
    Inventor: Nobuyoshi Takeuchi
  • Patent number: 5898614
    Abstract: A non-volatile semiconductor memory device comprises a plurality of memory cells each including a semiconductor substrate of a first conductivity type having a main surface region, a control gate portion formed in said main surface region of the semiconductor substrate and consisting of an impurity diffusion region of a second conductivity type opposite to said first conductivity type, a reading transistor portion formed on the main surface region of the substrate and consisting of a MOS type transistor structure, and a floating gate portion formed over the control gate portion and the reading transistor portion. These memory cells differ from each other in an overlapping area ratio Ap/An, where An denotes an area of an over-lapping portion between the floating gate and the impurity diffusion region of the control gate portion, Ap represents an area of an overlapping portion between the floating gate and an active region of the reading transistor portion.
    Type: Grant
    Filed: May 21, 1997
    Date of Patent: April 27, 1999
    Assignee: NKK Corporation
    Inventor: Nobuyoshi Takeuchi
  • Patent number: 5886927
    Abstract: One verify cell is connected to one word line, together with a plurality of array cells, and has a threshold value almost the same as the array cells. A write voltage or an erase voltage is applied to the array cells, setting the voltage applied to the verify cell at a small value, thereby electrically changing the threshold value of the verify cell. Alternatively, the sense ratio of a sense amplifier is changed with respect to the output of the verify cell and the output of a reference cell, thereby electrically changing the apparent threshold value of the verify cell. Data is thereby written into or erased from the array cells earlier than into or from the verify cell. Hence, the verification of the memory cells is accomplished by when the verify cell is verified.
    Type: Grant
    Filed: July 9, 1998
    Date of Patent: March 23, 1999
    Assignee: NKK Corporation
    Inventor: Nobuyoshi Takeuchi
  • Patent number: 5815433
    Abstract: A cell portion 10 of a MOS structure and a redundant cell portion 12 of an MNOS structure are formed in a single semiconductor substrate. These MOS and MNOS structures commonly include an oxide film 26. A laminate structure consisting of a silicon nitride film and a pad oxide film and used in the element separation step is included in the redundant cell portion 12. Therefore, the redundant circuit can be naturally formed without increasing the number of process steps, leading to a high yield without inviting an increase in the manufacturing cost.
    Type: Grant
    Filed: December 22, 1995
    Date of Patent: September 29, 1998
    Assignees: NKK Corporation, Macronix International Co., Ltd.
    Inventor: Nobuyoshi Takeuchi
  • Patent number: 5793078
    Abstract: According to the present invention, there is provided a non-volatile semiconductor memory device including a memory cell array in which a plurality of memory cells are arranged, wherein the memory cells contain two or more types of memory cells, which differs in gate couple ratio. Each memory cell includes source-drain regions provided apart from each other in a semiconductor substrate having a conductivity type, the source-drain regions having a conductivity type opposite to that of the semiconductor substrate, a floating gate provided above a channel region formed between the source-drain regions, and a control gate provided above a surface of the floating gate, and the memory cells contain two or more types of memory cells, which differ in relation to an area of a region in which the floating gate and the control gate overlap.
    Type: Grant
    Filed: May 21, 1997
    Date of Patent: August 11, 1998
    Assignee: NKK Corporation
    Inventor: Nobuyoshi Takeuchi
  • Patent number: 5766997
    Abstract: A field oxide is selectively formed on a silicon substrate. A first gate oxide is formed on the silicon substrate. Formed on the first gate oxide film is a floating gate which is comprised of a stack of a polysilicon film and a silicide layer with different thicknesses at different locations. Oxide spacer are formed on the side portions of the floating gate. A source region and a drain region are formed on the silicon substrate with a channel region disposed therebetween. Silicide layers are respectively formed on the source region and the drain region. The depth of the drain side silicide layer is shallower than the depth of the source side silicide layer. A step is provided on the surface of the floating gate. A control gate is formed on the floating gate via a gate insulator film.
    Type: Grant
    Filed: September 27, 1996
    Date of Patent: June 16, 1998
    Assignee: NKK Corporation
    Inventor: Nobuyoshi Takeuchi
  • Patent number: 5717400
    Abstract: A radar module includes a high-frequency signal generator comprising upper and lower parallel conductive plates, at least one dielectric rod held between the parallel conductive plates, a metal diode mount held between the parallel conductive plates, a gunn diode member mounted on a side of the diode mount, and a printed-circuit board mounted on the side of the diode mount in covering relationship to the gunn diode member and having a bias supply circuit on its surface for supplying a bias voltage to the gunn diode member. One terminal of the gunn diode member extends through a through hole defined in the printed-circuit board, is exposed in the vicinity of the surface of the diode mount, and is connected to the bias supply circuit.
    Type: Grant
    Filed: February 24, 1995
    Date of Patent: February 10, 1998
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Hiroshi Uematsu, Hiroyuki Ando, Tsutomu Yoneyama, Nobuyoshi Takeuchi, Shigeki Kato
  • Patent number: 5686022
    Abstract: A phosphorescent phosphor comprising a matrix expressed by M.sub.1-x Al.sub.2 O.sub.4-x (except X=0) in which M is at least one metal element selected from a group consisting of calcium, strontium and barium. X is in a range -0.33.ltoreq..times..ltoreq.0.60 (except x=0). Europium is doped to said matrix as an activator and at least one element selected from a group consisting of lanthanum, cerium, praseodymium, neodymium, samarium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium and lutetium is doped to said matrix as a co-activator. Magnesium is doped to M.
    Type: Grant
    Filed: October 18, 1995
    Date of Patent: November 11, 1997
    Assignee: Nemoto & Co., Ltd.
    Inventors: Yoshihiko Murayama, Nobuyoshi Takeuchi, Yasumitsu Aoki, Takashi Matsuzawa
  • Patent number: 5684739
    Abstract: A reference apparatus for determining a current or voltage of a semiconductor device, includes a plurality of reference cells having threshold values different from each other, and a selection circuit for selecting one of the plurality of reference cells. A current flowing in a semiconductor device can be determined by comparing the current flowing in the reference apparatus, with the current flowing in a semiconductor cell by means of a sense amplifier.
    Type: Grant
    Filed: November 30, 1995
    Date of Patent: November 4, 1997
    Assignee: NKK Corporation
    Inventor: Nobuyoshi Takeuchi
  • Patent number: 5661056
    Abstract: A tunnel oxide film is formed on the surface of a p-type silicon substrate, and a floating gate electrode made from a polysilicon film is formed on the surface of the tunnel oxide film. On the surface of the floating gate electrode, a control gate electrode is formed via an NON film formed by sequentially stacking a silicon nitride film, a silicon oxide film, and a silicon nitride film. A side oxide film is formed on the side surfaces of the floating gate electrode and the control gate electrode. Source and drain regions made from an n-type diffused layer are formed on the surfaces of element regions of the silicon substrate on the two sides of the floating gate electrodes.
    Type: Grant
    Filed: September 25, 1995
    Date of Patent: August 26, 1997
    Assignees: NKK Corporation, Macronix International Co., Ltd.
    Inventor: Nobuyoshi Takeuchi
  • Patent number: 5641696
    Abstract: The first impurity species having a low diffusion rate is heavily doped in a predetermined region of a semiconductor substrate in contact with portions corresponding to the edges of a floating gate, and the second impurity species having a low diffusion rate is lightly doped in the predetermined region from a position separated from the portions corresponding to the edges of the floating gate by a predetermined distance. Annealing is performed such that the second impurity species is diffused below the floating gate more inward than the first impurity species, and part of a diffusion region formed by the first impurity species serves as a tunnel region which overlaps the floating gate. With this structure, a short channel effect can be prevented, and an inter-band current can be suppressed.
    Type: Grant
    Filed: August 25, 1995
    Date of Patent: June 24, 1997
    Assignee: NKK Corporation
    Inventor: Nobuyoshi Takeuchi
  • Patent number: 5583396
    Abstract: A metal halide lamp is employed, as a light source, in an optical device such as, for example, an illuminator or an image display. The optical device includes a discharge tube filled with mercury, at least one rare gas, and at least one metal halide, and a pair of electrodes spaced from each other and enclosed in the discharge tube. The optical device also includes an electric circuit, electrically connected to the pair of electrodes, for starting the discharge tube by applying thereto a higher voltage than a voltage to be applied at a steady state to thereby cause an arc discharge in the discharge tube. When the lamp is turned off, power supply thereto from the electric circuit is temporarily interrupted, and when the lamp cools after a first time interval has elapsed subsequent to the interruption of the power supply, a starting voltage is applied to the lamp via the pair of electrodes for a second time interval to cause redischarge.
    Type: Grant
    Filed: March 17, 1994
    Date of Patent: December 10, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Omura Hideaki, Masayuki Wakamiya, Nobuyoshi Takeuchi, Munehiro Tabata
  • Patent number: 5512800
    Abstract: In a metal halide lamp container 1 sealed with mercury and rare gas, GdX.sub.3, LuX.sub.3, and CsX where halogen is iodine, bromine, or their mixture are sealed in a total weight of 1 mg/cc or more, with the weight of CsX defined within a range of 15% or more to 50% or less of the total halides, and the weight ratio of GdX.sub.3 and LuX.sub.3 is set in a range of 0.1.ltoreq.GdX.sub.3 /LuX.sub.3 .ltoreq.10. In addition to GdX.sub.3, LuX.sub.3, and CsX, at least one of thallium halide and dysprosium halide is added. Or DyX.sub.3, LuX.sub.3, NdX.sub.3, and CsX where halogen is iodine, bromine or their mixture are sealed in the specified total weight, with the weight ratio of CsX defined in the above range.
    Type: Grant
    Filed: July 13, 1994
    Date of Patent: April 30, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideaki Omura, Masayuki Wakamiya, Munehiro Tabata, Nobuyoshi Takeuchi
  • Patent number: 5424006
    Abstract: A phosphorescent phosphor according to the present invention includes a matrix expressed by MAl.sub.2 O.sub.4 in which M is at least one metal element selected from a group consisting of calcium, strontium and barium. Alternatively, a phosphorescent phosphor according to the present invention includes a matrix expressed by MAl.sub.2 O.sub.4 in which M is plural metal elements which are composed of magnesium and at least one metal element selected from a group consisting of calcium, strontium and barium and europium is added as an activator, further, co-activator is added.
    Type: Grant
    Filed: February 25, 1994
    Date of Patent: June 13, 1995
    Assignee: Nemoto & Co., Ltd.
    Inventors: Yoshihiko Murayama, Nobuyoshi Takeuchi, Yasumitsu Aoki, Takashi Matsuzawa
  • Patent number: 5394154
    Abstract: A radar module includes a high-frequency signal generator comprising upper and lower parallel conductive plates, at least one dielectric rod held between the parallel conductive plates, a metal diode mount held between the parallel conductive plates, a gunn diode member mounted on a side of the diode mount, and a printed-circuit board mounted on the side of the diode mount in covering relationship to the gunn diode member and having a bias supply circuit on its surface for supplying a bias voltage to the gunn diode member. One terminal of the gunn diode member extends through a through hole defined in the printed-circuit board, is exposed in the vicinity of the surface of the diode mount, and is connected to the bias supply circuit.
    Type: Grant
    Filed: September 10, 1993
    Date of Patent: February 28, 1995
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Hiroshi Uematsu, Hiroyuki Ando, Tsutomu Yoneyama, Nobuyoshi Takeuchi, Shigeki Kato
  • Patent number: 5223301
    Abstract: There is disclosed an improved surimi manufacturing process employing a mince crushing step that increases mince surface area to volume ratios. The effect of increasing surface area to volume ratios of mince particles, depending upon when in the surimi manufacturing process it is used, will improve overall yield of surimi and surimi by-products and/or reduce the requirement for fresh water for the surimi manufacturing process.
    Type: Grant
    Filed: March 12, 1992
    Date of Patent: June 29, 1993
    Assignee: Nichiro Corporation
    Inventors: Kazuaki Kanda, Kuninori Hanabusa, Nobuyoshi Takeuchi
  • Patent number: 5220166
    Abstract: An information reading method includes the steps of irradiating a phosphor activated by neodymium and ytterbium ions with exciting light of a wavelength between 500 nm and 780 nm that can excite the neodymium ions, and reading the information by receiving the light emitted from the phosphor with a photodetector designed to detect light with wavelengths between 840 m and 1100 nm. Consequently, the information recorded using the phosphor activated by neodymium and ytterbium ions can be read with a high performance without using a filter for cutting the exciting light.
    Type: Grant
    Filed: September 9, 1991
    Date of Patent: June 15, 1993
    Assignee: Nemoto & Co., Ltd.
    Inventors: Nobuyoshi Takeuchi, Yuzo Ishikawa, Kaori Kanesaka