Abstract: A semiconductor device of an embodiment includes a substrate, a first electrode, a second electrode, the first electrode provided between the substrate and the second electrode, the oxide semiconductor layer in contact with the first electrode, an oxide semiconductor layer between the first electrode and the second electrode, the oxide semiconductor layer contains Zn and at least one first element selected from In, Ga, Si, Al, and Sn; a conductive layer between the oxide semiconductor layer and the second electrode, the conductive layer in contact with the second electrode, the conductive layer contains O and at least one second element selected from the group consisting of In, Ga, Si, Al, Sn, Zn, and Ti, a gate electrode; and a gate insulating layer between the oxide semiconductor layer and the gate electrode.

Abstract: On a display panel 10, a first scanning signal line drive circuit 12 is formed along a side of a display region 11 and a second scanning signal line drive circuit 13 is formed along the opposite side by the same process as pixel circuits. The size of a transistor included, the width of a wiring line, or the like, differs between the first and second scanning signal line drive circuits 12 and 13, and the two scanning signal line drive circuits have different sizes in a lateral direction. By this, the center of the display region matches that of a non-integral-type display panel, ensuring compatibility with the non-integral-type display panel. Moreover, by suitably determining the widths of or spacings between wiring lines included in the two scanning signal line drive circuits, leakage between the wiring lines and breaks in the wiring lines are reduced, improving yield of display panels.

Abstract: On a display panel 10, a first scanning signal line drive circuit 12 is formed along a side of a display region 11 and a second scanning signal line drive circuit 13 is formed along the opposite side by the same process as pixel circuits. The size of a transistor included, the width of a wiring line, or the like, differs between the first and second scanning signal line drive circuits 12 and 13, and the two scanning signal line drive circuits have different sizes in a lateral direction. By this, the center of the display region matches that of a non-integral-type display panel, ensuring compatibility with the non-integral-type display panel. Moreover, by suitably determining the widths of or spacings between wiring lines included in the two scanning signal line drive circuits, leakage between the wiring lines and breaks in the wiring lines are reduced, improving yield of display panels.

Abstract: In an auxiliary capacitance electrode of each pixel region, a side end on one side in a direction in which a drain electrode crosses an end of a gate electrode so as to enter from the outside of the gate electrode to the inside thereof is disposed inside of an auxiliary capacitance line, and a side end on the other side in a direction in which the drain electrode crosses the end of the gate electrode so as to go out from the inside of the gate electrode to the outside thereof is disposed outside of the auxiliary capacitance line.

Abstract: A display device includes: a display panel (40a) having a plurality of display interconnects (3) provided so as to extend parallel to each other; a drive circuit (44a) provided on a side of one ends of the display interconnects (3), and connected to the display interconnects (3); a first interconnect path (Wa) and a second interconnect path (Wb) that are provided so as to cross the one ends of the display interconnects (3) in an insulating state; and a third interconnect path (Wc) that crosses the other ends of the display interconnects (3) in an insulating state, and is connected to the first interconnect path (Wa) and the second interconnect path (Wb). An amplifier circuit (A) is provided in a path including the first interconnect path (Wa) and the second interconnect path (Wb), and in a path including the first interconnect path (Wa) and the third interconnect path (Wc).

Abstract: In an auxiliary capacitance electrode of each pixel region, a side end on one side in a direction in which a drain electrode crosses an end of a gate electrode so as to enter from the outside of the gate electrode to the inside thereof is disposed inside of an auxiliary capacitance line, and a side end on the other side in a direction in which the drain electrode crosses the end of the gate electrode so as to go out from the inside of the gate electrode to the outside thereof is disposed outside of the auxiliary capacitance line.