Patents by Inventor Nobuyuki Hayama
Nobuyuki Hayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9076906Abstract: A hetero-junction bipolar phototransistor includes a photo-absorption layer formed of a first conductivity type semiconductor layer, and a collector operating as a barrier layer, a base layer, and an emitter layer, which are stacked in sequence on the photo-absorption layer. The photo-absorption layer, collector, base layer and emitter layer forms a first mesa structure, and an emitter contact layer forms a second mesa structure. The photo-absorption layer includes a semiconductor layer with a narrow gap corresponding to a light-sensing wavelength of the phototransistor. The collector includes a semiconductor layer with a wider gap than a gap of the photo-absorption layer. The base layer has an energy level equal to or higher than the energy level of the collector. The emitter layer has a wide gap as compared to the base layer, and an energy level in a valence band is lower than an energy level of the base layer.Type: GrantFiled: February 12, 2010Date of Patent: July 7, 2015Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGYInventors: Mutsuo Ogura, SungWoo Choi, Nobuyuki Hayama, Katsuhiko Nishida
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Publication number: 20110291158Abstract: The present invention provides a HPT having high sensitivity and extensive wavelength band characteristics. The collector and barrier layer (5) is formed on the photo-absorption layer (6), wherein the energy level in the conduction band is higher than that of the photo-absorption layer (6), the energy level in the valence band is almost equal to or higher than that of the photo-absorption layer (6) and is a relatively wider gap semiconductor than the photo-absorption layer. The base layer (4) formed on the collector and barrier layer (5), is a relatively narrow gap as compared with the collector and barrier layer (5), wherein the energy level in the conduction band is equal to or higher than that of the collector and barrier layer (5) in the boundary of the collector and barrier layer (5).Type: ApplicationFiled: February 12, 2010Publication date: December 1, 2011Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCCE AND TECHNOLOGYInventors: Mutsuo Ogura, SungWoo Choi, Nobuyuki Hayama, Katsuhiko Nishida
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Patent number: 6765241Abstract: A group III nitride semiconductor device of field effect transistor type having improved productivity, reduced parasitic capacitances adapted for excellent device performance in high-speed operation as well as good heat diffusion characteristics. The device includes an epitaxial growth layer of a group III nitride semiconductor with a buffer layer laid under it, formed on an A plane (an (11-20) plane) of a sapphire. Thereon a gate electrode, a source electrode, a drain electrode, and pad electrodes are formed, and a ground conductor layer is formed on the back face of the sapphire substrate. A thickness of said sapphire substrate tsub satisfies the following Equation (1).Type: GrantFiled: February 27, 2003Date of Patent: July 20, 2004Assignee: NEC CorporationInventors: Yasuo Ohno, Nobuyuki Hayama, Kensuke Kasahara, Tatsuo Nakayama, Hironobu Miyamoto, Yuji Takahashi, Yuji Ando, Kohji Matsunaga, Masaaki Kuzuhara
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Publication number: 20030151064Abstract: An object of the present invention is to improve, in a group III nitride semiconductor device, the productivity, the heat diffusion characteristic and the device performance in high-speed operation, and, therefor, in a group III nitride semiconductor device of the present invention, an epitaxial growth layer 13 of a group III nitride semiconductor with a buffer layer 12 laid under it is formed on a sapphire substrate 11 in which an A plane (an (11-20) plane) is set to be the principal plane, and thereon a gate electrode 16, a source electrode 15 and a drain electrode 17 are formed, wherein a thickness of the single crystalline sapphire substrate is specifically set to be 100 &mgr;m or less.Type: ApplicationFiled: February 27, 2003Publication date: August 14, 2003Inventors: Yasuo Ohno, Nobuyuki Hayama, Kensuke Kasahara, Tatsuo Nakayama, Hironobu Miyamoto, Yuji Takahashi, Yuji Ando, Kohji Matsunaga, Masaaki Kuzuhara
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Patent number: 6552373Abstract: A hetero-junction FET has an intermediate layer including n-type-impurity doped layer between an electron supply layer and an n-type cap layer. The intermediate layer cancels the polarized negative charge generated between the electron supply layer and the n-type cap layer by ionized positive charge, thereby reducing the barrier against the electrons and source/drain resistance.Type: GrantFiled: March 28, 2001Date of Patent: April 22, 2003Assignee: NEC CorporationInventors: Yuji Ando, Hironobu Miyamoto, Naotaka Iwata, Koji Matsunaga, Masaaki Kuzuhara, Kensuke Kasahara, Kazuaki Kunihiro, Yuji Takahashi, Tatsuo Nakayama, Nobuyuki Hayama, Yasuo Ohno
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Publication number: 20030034504Abstract: A semiconductor device is provided with a plurality of hetero junction bipolar transistors arranged in a specified direction. Also, the semiconductor device comprises emitter wiring connected to each emitter of the plural hetero junction bipolar transistors, collector wiring connected to each collector of said plural hetero junction bipolar transistors, and base wiring connected to at least one base of said plural hetero junction bipolar transistors. Bases that are not connected to the base wiring among the bases of the plural hetero junction bipolar transistors are connected to the emitter wiring.Type: ApplicationFiled: October 11, 2002Publication date: February 20, 2003Inventors: Kouji Azuma, Nobuyuki Hayama, Norio Goto
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Patent number: 6507089Abstract: A semiconductor device is provided with a plurality of hetero junction bipolar transistors arranged in a specified direction. Also, the semiconductor device comprises emitter wiring connected to each emitter of the plural hetero junction bipolar transistors, collector wiring connected to each collector of said plural hetero junction bipolar transistors, and base wiring connected to at least one base of said plural hetero junction bipolar transistors. Bases that are not connected to the base wiring among the bases of the plural hetero junction bipolar transistors are connected to the emitter wiring.Type: GrantFiled: June 7, 2000Date of Patent: January 14, 2003Assignee: NEC CorporationInventors: Kouji Azuma, Nobuyuki Hayama, Norio Goto
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Patent number: 6492669Abstract: A carrier travel layer is formed on the substrate of a semiconductor device with a buffer layer interposed, and a spacer layer and carrier supply layer are then formed on this carrier travel layer. On the carrier supply layer are provided a source electrode and a drain electrode, and a gate electrode is provided on an interposed Schottky layer. The carrier supply layer is composed of AlGaN and has tensile strain. The Schottky layer is composed of InGaN and has compressive strain. A negative piezoelectric charge is induced on the carrier supply layer side of the Schottky layer, and a positive piezoelectric charge is induced on the opposite side of the Schottky layer, whereby a sufficient Schottky barrier height is obtained and leakage current is suppressed.Type: GrantFiled: June 28, 2001Date of Patent: December 10, 2002Assignee: NEC CorporationInventors: Tatsuo Nakayama, Yuji Ando, Hironobu Miyamoto, Kazuaki Kunihiro, Yuji Takahashi, Kensuke Kasahara, Nobuyuki Hayama, Yasuo Ohno, Kouji Matsunaga, Masaaki Kuzuhara
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Patent number: 6465814Abstract: A semiconductor device of the present invention comprises Al0.3Ga0.7N layer 4 and Al0.1Ga0.9N layer 5 having different Al contents as an electron supply layer on GaN layer 6 serving as an active layer. An area where Al0.3Ga0.7N layer 4 is formed is used as a low resistance area, while an area where Al0.1Ga0.9N layer 5 is formed is used as a high resistance area. As a result, a distribution of two-dimensional electrons serving as carriers is produced within a horizontal plane perpendicular to the thickness direction of the layers to form a desired device configuration. For example, when the configuration is applied to a transistor configuration, a channel concentration under a gate is reduced to improve withstand voltage between the gate and a drain, and at the same time, a channel concentration in source and drain areas is increased to realize low contact resistance.Type: GrantFiled: June 27, 2001Date of Patent: October 15, 2002Assignee: NEC CorporationInventors: Kensuke Kasahara, Yasuo Ohno, Masaaki Kuzuhara, Hironobu Miyamoto, Yuji Ando, Tatsuo Nakayama, Kazuaki Kunihiro, Nobuyuki Hayama, Yuji Takahashi, Kouji Matsunaga
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Patent number: 6441391Abstract: An object of the present invention is to improve, in a group III nitride semiconductor device, the productivity, heat radiation characteristic and performance in the element high speed operation; upon a sapphire substrate in which an A plane (an (11-20) plane) is set to be the basal plane, an epitaxial growth layer of a group III nitride semiconductor is formed and, thereon, a gate electrode 16, a source electrode 15 and a drain electrode 17 are formed; these electrodes are disposed in such a way that a direction along which they are laid makes an angle within 20° with respect to a C axis of sapphire.Type: GrantFiled: August 29, 2001Date of Patent: August 27, 2002Assignee: NEC CorporationInventors: Yasuo Ohno, Nobuyuki Hayama, Kensuke Kasahara, Tatsuo Nakayama, Hironobu Miyamoto, Yuji Takahashi, Yuji Ando, Kohji Matsunaga, Masaaki Kuzuhara
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Patent number: 6440822Abstract: In a method of manufacturing a semiconductor device, trench sections are formed on a side of one of opposing surface portions of a substrate. At lest a part of each of the trench sections is covered by a power supply metal layer which is formed on the one surface portion of the substrate. The substrate is fixed to a support such that the one surface of the substrate fits to the support. A chip is separated from the substrate using the trench sections. A conductive film is formed on side surface portions of the chip and the other surface portion of the chip. Then, the chip is separated from the support.Type: GrantFiled: July 9, 2001Date of Patent: August 27, 2002Assignee: NEC CorporationInventors: Nobuyuki Hayama, Masaaki Kuzuhara, Kouji Matsunaga, Tatsuo Nakayama, Yuji Takahashi, Yasuo Ohno, Kazuaki Kunihiro, Kensuke Kasahara, Hironobu Miyamoto, Yuji Ando
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Publication number: 20020048889Abstract: In a method of manufacturing a semiconductor device, trench sections are formed on a side of one of opposing surface portions of a substrate. At least a part of each of the trench sections is covered by a power supply metal layer which is formed on the one surface portion of the substrate. The substrate is fixed to a support such that the one surface of the substrate fits to the support. A chip is separated from the substrate using the trench sections. A conductive film is formed on side surface portions of the chip and the other surface portion of the chip. Then, the chip is separated from the support.Type: ApplicationFiled: July 9, 2001Publication date: April 25, 2002Applicant: NEC CorporationInventors: Nobuyuki Hayama, Masaaki Kuzuhara, Kouji Matsunaga, Tatsuo Nakayama, Yuji Takahashi, Yasuo Ohno, Kazuaki Kunihiro, Kensuke Kasahara, Hironobu Miyamoto, Yuji Ando
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Publication number: 20020047113Abstract: An object of the present invention is to improve, in a group III nitride semiconductor device, the productivity, heat radiation characteristic and performance in the element high speed operation; upon a sapphire substrate in which an A plane (an (11-20) plane) is set to be the basal plane, an epitaxial growth layer of a group III nitride semiconductor is formed and, thereon, a gate electrode 16, a source electrode 15 and a drain electrode 17 are formed; these electrodes are disposed in such a way that a direction along which they are laid makes an angle within 20° with respect to a C axis of sapphire.Type: ApplicationFiled: August 29, 2001Publication date: April 25, 2002Applicant: NEC CORPORATIONInventors: Yasuo Ohno, Nobuyuki Hayama, Kensuke Kasahara, Tatsuo Nakayama, Hironobu Miyamoto, Yuji Takahashi, Yuji Ando, kohji Matsunaga, Masaaki Kuzuhara
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Publication number: 20020017696Abstract: A carrier travel layer is formed on the substrate of a semiconductor device with a buffer layer interposed, and a spacer layer and carrier supply layer are then formed on this carrier travel layer. On the carrier supply layer are provided a source electrode and a drain electrode, and a gate electrode is provided on an interposed Schottky layer. The carrier supply layer is composed of AlGaN and has tensile strain. The Schottky layer is composed of InGaN and has compressive strain. A negative piezoelectric charge is induced on the carrier supply layer side of the Schottky layer, and a positive piezoelectric charge is induced on the opposite side of the Schottky layer, whereby a sufficient Schottky barrier height is obtained and leakage current is suppressed.Type: ApplicationFiled: June 28, 2001Publication date: February 14, 2002Inventors: Tatsuo Nakayama, Yuji Ando, Hironobu Miyamoto, Kazuaki Kunihiro, Yuji Takahashi, Kensuke Kasahara, Nobuyuki Hayama, Yasuo Ohno, Kouji Matsunaga, Masaaki Kuzuhara
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Publication number: 20020017648Abstract: A semiconductor device of the present invention comprises Al0.3Ga0.7N layer 4 and Al0.1Ga0.9N layer 5 having different Al contents as an electron supply layer on GaN layer 6 serving as an active layer. An area where Al0.3Ga0.7N layer 4 is formed is used as a low resistance area, while an area where Al0.1Ga0.9N layer 5 is formed is used as a high resistance area. As a result, a distribution of two-dimensional electrons serving as carriers is produced within a horizontal plane perpendicular to the thickness direction of the layers to form a desired device configuration. For example, when the configuration is applied to a transistor configuration, a channel concentration under a gate is reduced to improve withstand voltage between the gate and a drain, and at the same time, a channel concentration in source and drain areas is increased to realize low contact resistance.Type: ApplicationFiled: June 27, 2001Publication date: February 14, 2002Inventors: Kensuke Kasahara, Yasuo Ohno, Masaaki Kuzuhara, Hironobu Miyamoto, Yuji Ando, Tatsuo Nakayama, Kazuaki Kunihiro, Nobuyuki Hayama, Yuji Takahashi, Kouji Matsunaga
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Publication number: 20010040247Abstract: A hetero-junction FET has an intermediate layer including n-type-impurity doped layer between an electron supply layer and an n-type cap layer. The intermediate layer cancels the polarized negative charge generated between the electron supply layer and the n-type cap layer by ionized positive charge, thereby reducing the barrier against the electrons and source/drain resistance.Type: ApplicationFiled: March 28, 2001Publication date: November 15, 2001Inventors: Yuji Ando, Hironobu Miyamoto, Naotaka Iwata, Koji Matsunaga, Masaaki Kuzuhara, Kensuke Kasahara, Kazuaki Kunihiro, Yuji Takahashi, Tatsuo Nakayama, Nobuyuki Hayama, Yasuo Ohno
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Patent number: 4217783Abstract: A pressure sensor comprises essentially magnetoresistive elements formed on a diaphragm serving as a stress magnifier. The diaphragm may be made, for example, of glass in a thickness of 0.5 millimeter, and the magnetoresistive elements can be formed thereon in any desired pattern of thin stripes by ordinary thin-film techniques. Such sensor elements can be mass produced, e.g., by vapor deposition and etching on a large sheet of diaphragm material and cutting into chips of desired shape and size.Type: GrantFiled: February 15, 1979Date of Patent: August 19, 1980Assignee: Nippon Electric Company, Ltd.Inventors: Susumu Ito, Morimasa Nagao, Toshio Yamagata, Nobuyuki Hayama