Abstract: In a circuit design method, an arrangement/wiring section (112) determines an arrangement and wiring of logical blocks (40a, 40b, 40c, 40d) so that delay limitation information about input signals supplied to the logical blocks (40a, 40b, 40c, 40d) and limitation conditions about a difference of delay times among a pre-charge control signal (ck0, ck1, ck2) supplied to the corresponding logical lock (40a, 40b, 40c, 40d) and the input signals are satisfied.

Abstract: In a circuit design method, an arrangement/wiring section (112) determines an arrangement and wiring of logical blocks (40a, 40b, 40c, 40d) so that delay limitation information about input signals supplied to the logical blocks (40a, 40b, 40c, 40d) and limitation conditions about a difference of delay times among a pre-charge control signal (ck0, ck1, ck2) supplied to the corresponding logical block (40a, 40b, 40c, 40d) and the input signals are satisfied.

Abstract: In a memory composed of a plurality of banks, even if succeeding access is performed to the same bank as that being currently accessed, the succeeding access can be controlled according to the destination which is currently accessed and its accessed state. In addition, if particular relationships exist between a precedingly accessed destination and the succeedingly accessed destination, a corresponding main word line out of main word lines which correspond to respective rows of respective banks can be still held in its selected state even after the preceding access has been terminated.

Abstract: An LCD panel capable of displaying three-dimensional images has, for each pixel, a transparent part and an opaque active element region. The active element region includes an input unit for receiving depth data including at least a depth and supplying the depth data to the pixel, a holder (Zc) for holding depth data, and a determination unit for determining which one of the depth data provided by the input unit and stored in the holder (Zc) is shallower, i.e., closer to a display screen than the other. The determined depth is used to display an object on the pixel.

Abstract: A data processing device including: data processor handling at one time a plurality of data such as instructions each consisting of one word; a plurality of input ports for inputting a plurality of data; a memory for storing temporarily the data inputted through the input pins, each of whose elements consisting of one byte; and exclusive OR gates for designating each of the elements of the memory. Each portion of a memory element is referenced by a byte address each consisting two bits wherein when the information device can handle data formed in a Little-endian-type, in which the address are increased in sequence from the byte on the Least significant Bit (LSB), and the data is formed in a big-endian-type, in which the byte address are increased in sequence from the byte on the Most Significant Bit (MSB), the exclusive OR gates reverse some of the bits of each byte address.

Abstract: A multiport cache memory for exchanging data or instructions with a plurality of arithmetic circuitries independently according to a load instruction or a store instruction provided from a CPU. The cache memory comprises a plurality of read only ports for respectively transmitting data or instructions to each arithmetic circuit according to the load instruction, and a plurality of read/write ports for respectively transmitting the data or the instructions from to each arithmetic circuit according to the load or store instruction.

Abstract: A microprocessor includes an integer processing unit with the decimal point fixed; first and second floating point processing units which can execute simultaneously with the integer processing unit; a register file; a first fixed point processing unit for receiving data at the point n from the register file, for searching for data at the point n+1 by partitioned addition of the increment forwarding by one point, and for outputting the searched data; a second fixed point processing unit for receiving data at the point n from the register file, for searching for data at the point n+2 by partitioned addition of the increment forwarding by two points, and for outputting the searched data; and a merger for receiving the addition results and for gathering data of the bit length of each upper half.

Abstract: A multiport cache memory control unit includes a central processing unit having N arithmetic units for executing arithmetic processing, a tag memory having N address ports for storing addresses, a multiport cache memory having N data ports for storing pieces of data at addresses which agree with the addresses stored in the tag memory, and a snoop address port through which a snoop operation is executed to detect an address signal. Arithmetic processing is executed in each of the arithmetic units by reading a piece of data from the cache memory after providing an address signal to the tag memory to check whether or not the data is stored in the cache memory. In cases where a cache miss occurs, a piece of data stored in a main memory unit is fetched through the snoop address port without halting the arithmetic processing.

Abstract: A three-dimensional graphic processing apparatus includes n arithmetic ICs (Integrated Circuits) for performing linear interpolation calculations for each scan line of a triangle polygon to obtain intensity values and depth coordinate values of pixels, and two types of n memories for storing the calculation results. The n arithmetic ICs parallelly execute linear interpolation calculations of n different pixels successive on a single scan line of a single triangle polygon in one processing cycle. Each arithmetic IC calculates for each of every n pixels in one processing cycle, and a corresponding one of the memories stores the calculation result.

Abstract: Depth information is stored in a 2-port memory having a random port and a serial port. The depth information is read out from the serial port of the 2-port memory and is supplied to an integrated circuit. The integrated circuit performs pipeline processing by using the depth information read out from the 2-port memory. If write-in is necessary as a result of the pipeline processing, the processed depth information is supplied to the random port of the 2-port memory, and the depth information is stored once again in the 2-port memory.

Abstract: A memory cell contains a first MOS transistor, a second MOS transistor, and a capacitor, which are connected at the first ends to one another. A word line for a first cell series, is connected to the gates of first MOS transistors in the memory cells arrayed in a row. A word line for a second cell series, is connected to the gates of second MOS transistors arrayed in a column. A bit line for the first cell series, is connected to the second ends of the first MOS transistors in the row. A bit line for the second cell series, is connected to the second ends of the second MOS transistors in the column. A selection circuit selects the first cell series or the second cell series, according to an external input signal for cell series selection. According to the semiconductor memory deivce, one of the first and second cell array series of the memory cell array can be accessed according to a logic level of the array series select signal.

Abstract: In a prehcarge-type carry chained adder circuit, stages as represented by adders are grouped into a plurality of blocks each consisting of a plurality of stages. When the propagating functions of the stages of each block are active, a carry signal reproduced from the preceding block is transferred to the succeeding blocks through a bypass circuit.

Abstract: A multiplier array circuit including decoders for decoding a multiplier on the basis of Booth's algorithm; cell array blocks for receiving the selection signals from the decoders and a multiplicand and performing the multiplication of the multiplicand and the multiplier on the basis of Booth's algorithm; and an adder for obtaining the final products on the basis of the outputs from the cell array blocks. In order to enable the functionally divisional operation, the cell array blocks includes complex cells which operate as the basic cells in the non-division mode and which operate as the code cells in the division mode.

Abstract: A binary data identification circuit including first and second potential terminals set to first and second logical potential levels, a series circuit including first to (n-1)th transfer gates whose conduction states are controlled responsive to 1st to (n-1)th bit signals of an input operand containing first to nth bit signals, one end of the series circuit being connected to the first potential terminal, nth to (2n-2)th transfer gates which are controlled, responsive to the first to (n-1)th bit signals, so as to have opposite conduction states with respect to those of the first to (n-1)th transfer gates, the nth to (2n-2)th transfer gates being connected at their source to the second potential terminal and at their drain to the drains of the first to (n-1)th transfer gates; and first to nth logic gates whose first input terminals receive the first to nth bit signals and whose second terminals are connected to the first potential terminal and to the drains of the first to (n-1)th transfer gates, the first to