Patents by Inventor Nobuyuki Iriki

Nobuyuki Iriki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7130063
    Abstract: A test pattern formed in a scribe line area of a wafer is irradiated with a light beam to measure the width thereof; the test pattern is irradiated with an electron beam so as to measure the width thereof; an amount of change in the width of the test pattern is calculated; a dummy pattern having the same width as that of a semiconductor device of the wafer is irradiated with an electron beam to measure the width thereof; and the width of a pattern is estimated by the use of the calculated amount of width change so as to determine the shape of the pattern. Thus, a shape measuring system and method capable of determining the shape of a micropattern in a semiconductor device without changing the dimensions of the micropattern can be provided.
    Type: Grant
    Filed: April 11, 2005
    Date of Patent: October 31, 2006
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Yasuhiro Mitsui, Yasutsugu Usami, Isao Kawata, Yuya Toyoshima, Tadashi Otaka, Nobuyuki Iriki
  • Publication number: 20050182595
    Abstract: A test pattern formed in a scribe line area of a wafer is irradiated with a light beam to measure the width thereof; the test pattern is irradiated with an electron beam so as to measure the width thereof; an amount of change in the width of the test pattern is calculated; a dummy pattern having the same width as that of a semiconductor device of the wafer is irradiated with an electron beam to measure the width thereof; and the width of a pattern is estimated by the use of the calculated amount of width change so as to determine the shape of the pattern. Thus, a shape measuring system and method capable of determining the shape of a micropattern in a semiconductor device without changing the dimensions of the micropattern can be provided.
    Type: Application
    Filed: April 11, 2005
    Publication date: August 18, 2005
    Inventors: Yasuhiro Mitsui, Yasutsugu Usami, Isao Kawata, Yuya Toyoshima, Tadashi Otaka, Nobuyuki Iriki
  • Patent number: 6894790
    Abstract: A test pattern formed in a scribe line area of a wafer is irradiated with a light beam to measure the width thereof; the test pattern is irradiated with an electron beam so as to measure the width thereof; an amount of change in the width of the test pattern is calculated; a dummy pattern having the same width as that of a semiconductor device of the wafer is irradiated with an electron beam to measure the width thereof; and the width of a pattern is estimated by the use of the calculated amount of width change so as to determine the shape of the pattern. Thus, a shape measuring system and method capable of determining the shape of a micropattern in a semiconductor device without changing the dimensions of the micropattern can be provided.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: May 17, 2005
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Yasuhiro Mitsui, Yasutsugu Usami, Isao Kawata, Yuya Toyoshima, Tadashi Otaka, Nobuyuki Iriki
  • Patent number: 6716648
    Abstract: The efficiency is improved for a lithography step in a process of manufacturing semiconductor integrated circuits. For each semiconductor wafer, the method has a step of depositing a photosensitive organic film, a step of performing exposure processing, a step of performing development processing, a step of conducting a test, and a consistent processing step for removing the photosensitive organic film of a semiconductor wafer determined as nonstandard in the test in the processing unit for depositing the photosensitive organic film, and returning again to the step of depositing the photosensitive organic film to regenerate the semiconductor wafer. During the regeneration processing for the semiconductor wafer, other processing is automatically performed in parallel for other semiconductor wafers of the plurality of semiconductor wafers in a system for performing the consistent processing.
    Type: Grant
    Filed: December 26, 2001
    Date of Patent: April 6, 2004
    Assignee: Renesas Technology Corp.
    Inventor: Nobuyuki Iriki
  • Publication number: 20030090684
    Abstract: A test pattern formed in a scribe line area of a wafer is irradiated with a light beam to measure the width thereof; the test pattern is irradiated with an electron beam so as to measure the width thereof; an amount of change in the width of the test pattern is calculated; a dummy pattern having the same width as that of a semiconductor device of the wafer is irradiated with an electron beam to measure the width thereof; and the width of a pattern is estimated by the use of the calculated amount of width change so as to determine the shape of the pattern. Thus, a shape measuring system and method capable of determining the shape of a micropattern in a semiconductor device without changing the dimensions of the micropattern can be provided.
    Type: Application
    Filed: November 12, 2002
    Publication date: May 15, 2003
    Inventors: Yasuhiro Mitsui, Yasutsugu Usami, Isao Kawata, Yuya Toyoshima, Tadashi Otaka, Nobuyuki Iriki
  • Publication number: 20020081758
    Abstract: The efficiency is improved for a lithography step in a process of manufacturing semiconductor integrated circuits. For each semiconductor wafer, the method has a step of depositing a photosensitive organic film, a step of performing exposure processing, a step of performing development processing, a step of conducting a test, and a consistent processing step for removing the photosensitive organic film of a semiconductor wafer determined as nonstandard in the test in the processing unit for depositing the photosensitive organic film, and returning again to the step of depositing the photosensitive organic film to regenerate the semiconductor wafer. During the regeneration processing for the semiconductor wafer, other processing is automatically performed in parallel for other semiconductor wafers of the plurality of semiconductor wafers in a system for performing the consistent processing.
    Type: Application
    Filed: December 26, 2001
    Publication date: June 27, 2002
    Inventor: Nobuyuki Iriki
  • Patent number: 5497331
    Abstract: A semiconductor integrated circuit device fabrication technique improves the accuracy of element qualities by considering the influence of interaction of element quality parameters in the quality control of semiconductor fabrication processes and also by improving the product yield estimation accuracy so that the production efficiency can be improved. An initial value of a membership function is first set and then a plurality of element quality parameters and a combined quality parameter are expressed by membership functions in fuzzy control in a semiconductor fabrication apparatus for automating a fabrication method by connecting a computer with various measuring instruments and various processors by communication devices.
    Type: Grant
    Filed: June 8, 1994
    Date of Patent: March 5, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Nobuyuki Iriki, Tsutomu Okabe, Kenji Watanabe, Hisashi Maejima, Shinji Kuniyoshi
  • Patent number: 5432608
    Abstract: According to the present invention, in making alignment between a semiconductor integrated circuit wafer and a mask or a reticle in light exposure of the wafer with a monochromatic light such as g-, i- or h-line of a mercury lamp, using a reduced stepping exposure system, light from a predetermined pattern on the wafer is taken out to an off-axis position and observed according to Through-the-Lens method; in this case as a characteristic feature of the invention, the observation light taken out from below the reticle is passed through chromatic aberration correcting lenses, thereby permitting the use of a polychromatic or continuous spectrum light.
    Type: Grant
    Filed: August 24, 1993
    Date of Patent: July 11, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Susumu Komoriya, Takao Kawanabe, Shinya Nakagawa, Takayoshi Oosakaya, Nobuyuki Iriki
  • Patent number: 5260771
    Abstract: According to the present invention, in making alignment between a semiconductor integrated circuit wafer and a mask or a reticle in light exposure of the wafer with a monochromatic light such as g-, i- or h-line of a mercury lamp, using a reduced stepping exposure system, light from a predetermined pattern on the wafer is taken out to an off-axis position and observed according to a through-the-lens method; in this case as a characteristic feature of the invention, the, observation light is taken out from below the reticle and is passed through chromatic aberration correcting lenses, thereby permitting the use of a polychromatic or continuous spectrum light.
    Type: Grant
    Filed: December 20, 1991
    Date of Patent: November 9, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Susumu Komoriya, Takao Kawanabe, Shinya Nakagawa, Takayoshi Oosakaya, Nobuyuki Iriki
  • Patent number: 5094539
    Abstract: According to the present invention, in making alignment between a semiconductor integrated circuit wafer and a mask or a reticle in light exposure of the wafer with a monochromatic light such as g-, i- or h- line of a mercury lamp, using a reduced stepping exposure system, light from a predetermined pattern on the wafer is taken out to an off-axis position and observed according to a through-the-lens method; in this case as a characteristic feature of the invention, the observation light is taken out from below the reticle and is passed through chromatic aberration correcting lenses, thereby permitting the use of a polychromatic or continuous spectrum light.
    Type: Grant
    Filed: February 21, 1989
    Date of Patent: March 10, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Susumu Komoriya, Takao Kawanabe, Shinya Nakagawa, Takayoshi Oosakaya, Nobuyuki Iriki