Patents by Inventor Nobuyuki Kasai
Nobuyuki Kasai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11971566Abstract: A laminate including a horizontally oriented liquid crystal cured film that is a cured material of a polymerizable liquid crystal composition containing at least one type of polymerizable liquid crystal compound, and a vertically oriented liquid crystal cured film is provided. The horizontally oriented liquid crystal cured film is the cured material of the polymerizable liquid crystal composition in which the polymerizable liquid crystal compound is cured in a state of being horizontally oriented with respect to a plane of the liquid crystal cured film, and satisfies the following formulae: nxA(450)>nyA(450)>nzA(450) and ReA(450)/ReA(550)<1.00.Type: GrantFiled: July 17, 2019Date of Patent: April 30, 2024Assignee: SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Tatsuaki Kasai, Nobuyuki Hatanaka
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Patent number: 9620289Abstract: According to an embodiment, first and second internal electrode layers are alternatively interposed between dielectric layers to form a laminated capacitor. The first internal electrode layer have a first base portion connected to a first external electrode, and is extended from the first base portion toward a second external electrode. The second internal electrode layer have a base portion connected to the second external electrode, and is extended from the second external electrode toward the first external electrode. The second internal electrode layer is formed in a deformation pattern which allows a path length greater than a length between the first and the second external electrode so that an open stub producing an open stub resonance is formed.Type: GrantFiled: September 2, 2014Date of Patent: April 11, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Yasuki Torigoshi, Nobuyuki Kasai
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Publication number: 20150146344Abstract: According to an embodiment, first and second internal electrode layers are alternatively interposed between dielectric layers to form a laminated capacitor. The first internal electrode layer have a first base portion connected to a first external electrode, and is extended from the first base portion toward a second external electrode. The second internal electrode layer have a base portion connected to the second external electrode, and is extended from the second external electrode toward the first external electrode. The second internal electrode layer is formed in a deformation pattern which allows a path length greater than a length between the first and the second external electrode so that an open stub producing an open stub resonance is formed.Type: ApplicationFiled: September 2, 2014Publication date: May 28, 2015Inventors: Yasuki Torigoshi, Nobuyuki Kasai
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Patent number: 7760233Abstract: A portable terminal has an imaging section, a storage section that stores an image picked up by the imaging section, a radio section that transmits and receives data through a communication network, and a control section that controls the imaging section and the radio section. When the radio section receives an e-mail, the control section extracts an instruction information from the e-mail, controls the imaging section to pick up an image, determines the timing of transmitting the picked-up image to a predetermined destination based on the instruction information, and controls the radio section to transmit the picked-up image at the determined timing.Type: GrantFiled: December 17, 2004Date of Patent: July 20, 2010Assignee: Kyocera CorporationInventor: Nobuyuki Kasai
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Patent number: 7678596Abstract: First and second semiconductor lasers interelement-separated from each other are formed. Total thickness of a fourth upper cladding layer and a second contact layer of the second semiconductor laser is smaller than total thickness of a second upper cladding layer and the first contact layer of the first semiconductor laser. First and second ridges are formed in the first and second semiconductor lasers by dry etching, using a resist as a mask, and the dry etching is stopped when a second etching stopper layer is exposed at the second ridge. The second upper cladding layer remaining on a first etching stopper layer at the first ridge is selectively removed by wet etching, using the resist as a mask.Type: GrantFiled: February 29, 2008Date of Patent: March 16, 2010Assignee: Mitsubishi Electric CorporationInventor: Nobuyuki Kasai
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Publication number: 20090093076Abstract: First and second semiconductor lasers interelement-separated from each other are formed. Total thickness of a fourth upper cladding layer and a second contact layer of the second semiconductor laser is smaller than total thickness of a second upper cladding layer and the first contact layer of the first semiconductor laser. First and second ridges are formed in the first and second semiconductor lasers by dry etching, using a resist as a mask, and the dry etching is stopped when a second etching stopper layer is exposed at the second ridge. The second upper cladding layer remaining on a first etching stopper layer at the first ridge is selectively removed by wet etching, using the resist as a mask.Type: ApplicationFiled: February 29, 2008Publication date: April 9, 2009Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Nobuyuki Kasai
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Publication number: 20050134694Abstract: A portable terminal has an imaging section, a storage section that stores an image picked up by the imaging section, a radio section that transmits and receives data through a communication network, and a control section that controls the imaging section and the radio section. When the radio section receives an e-mail, the control section extracts an instruction information from the e-mail, controls the imaging section to pick up an image, determines the timing of transmitting the picked-up image to a predetermined destination based on the instruction information, and controls the radio section to transmit the picked-up image at the determined timing.Type: ApplicationFiled: December 17, 2004Publication date: June 23, 2005Inventor: Nobuyuki Kasai
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Publication number: 20020196828Abstract: In a semiconductor laser device including a window structure region formed by disordering an active layer or active layers of a quantum well structure by silicon ion implantation and a subsequent heat treatment, a dislocation loop is substantially absent in the window structure region and the vicinity thereof (upper clad layer). Accordingly, deterioration of the semiconductor laser device induced by dislocation loops can be prevented, and reliability of the semiconductor laser device can be improved.Type: ApplicationFiled: May 2, 2002Publication date: December 26, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Shinji Abe, Tetsuya Yagi, Motoharu Miyashita, Harumi Nishiguchi, Yuji Ohkura, Nobuyuki Kasai, Yoshihisa Tashiro, Junji Tanimura
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Patent number: 5917231Abstract: A resin-encapsulated semiconductor device includes a semi-conductor substrate having a surface including an insulating film and an electroplated transmission line. To avoid a possible separation and/or peeling of the insulating film with respect to the substrate, a gap is present between the insulating film and the plated line.Type: GrantFiled: July 9, 1997Date of Patent: June 29, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Nobuyuki Kasai
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Patent number: 5888859Abstract: A method of making a semiconductor device includes forming a recess in a compound semiconductor substrate using a patterned insulating film on a surface of the substrate, implanting dopant ions at the bottom of the recess to form a channel region, and depositing a refractory metal film. The refractory metal film is etched, using a resist pattern, to form a gate electrode and additional dopant ions are implanted to form relatively highly doped regions intersecting the channel region. Very highly doped regions are formed my implantation, after removing the insulating film, using the gate electrode and remainder of the resist mask as an implantation mask. After stripping the resist, annealing to activate the implanted ions, and depositing a passivating film on the substrate and gate electrode, source and drain electrodes are formed.Type: GrantFiled: November 15, 1996Date of Patent: March 30, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tomoki Oku, Shinichi Miyakuni, Nobuyuki Kasai, Yasutaka Kohno, deceased
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Patent number: 5675159Abstract: A semiconductor device includes a compound semiconductor body having a recess, the recess having a bottom and a hollow, and a refractory metal gate electrode having a lower portion within the hollow. The compound semiconductor body includes a compound semiconductor substrate; a channel layer including a compound semiconductor of a first conductivity type, the channel layer being located on the substrate between the gate electrode and the substrate; first active layers of the compound semiconductor and of the first conductivity type located on regions of the substrate in the recess where the channel layer is not present; and second active layers of the compound semiconductor and of the first conductivity type located on regions of the substrate in the recess where the channel layer is not present; and second active layers of the compound semiconductor of the first conductivity type located on regions of the substrate sandwiching the recess.Type: GrantFiled: January 5, 1996Date of Patent: October 7, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tomoki Oku, Nobuyuki Kasai
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Patent number: 5648668Abstract: A semiconductor device includes a drain electrode, a source electrode, and a gate electrode on a semiconductor substrate; a semiconductor layer on a region of the semiconductor substrate and including a first dopant concentration region on which the gate electrode is centrally disposed; a second dopant concentration region more heavily doped than the first dopant concentration region, disposed adjacent the first dopant concentration region and having a length toward the drain electrode; third dopant concentration regions, more heavily doped than the second dopant concentration region, respectively disposed adjacent the second dopant concentration region at drain side and adjacent the first dopant concentration region at the source side; a drain electrode disposed on one of the third dopant concentration regions; and a source electrode disposed on the other of the third dopant concentration regions.Type: GrantFiled: October 31, 1995Date of Patent: July 15, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Nobuyuki Kasai
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Patent number: 5288654Abstract: A mushroom-shaped gate electrode has a lower end in a recess in a semiconductor active layer on a semiconductor substrate. The gate electrode has an enlarged head. A metallic side wall is disposed on a portion of the leg of the gate electrode adjacent the head. Thus, the gate length of a semiconductor device, such as a field effect transistor, is reduced while the effective cross-sectional area of the gate electrode is increased whereby the noise characteristics of the semiconductor device are improved.Type: GrantFiled: February 8, 1993Date of Patent: February 22, 1994Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Nobuyuki Kasai, Shinichi Sakamoto, Takuji Sonoda, Tetsuya Yagi
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Patent number: 5250822Abstract: A field effect transistor includes a GaAs substrate on which an undoped GaAs layer is disposed. A doped electron supply layer is disposed on the undoped GaAs layer and has a negligible deep dopant level. A channel layer disposed on the electron supply layer has a larger electron affinity than the electron supply layer. The electron supply layer and the channel layer form a heterojunction. A third semiconductor layer having the same conductivity type as the electron supply layer is disposed on the electron supply layer. Gate, drain, and source electrodes are disposed on the third semiconductor layer. The dopant concentration of the third layer is smaller than the dopant concentration of the electron supply layer.Type: GrantFiled: March 25, 1992Date of Patent: October 5, 1993Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takuji Sonoda, Shinichi Sakamoto, Nobuyuki Kasai
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Patent number: 5220186Abstract: A mushroom-shaped gate electrode has a lower end in a recess in a semiconductor active layer on a semiconductor substrate. The gate electrode has an enlarged head. A metallic side wall is disposed on a portion of the leg of the gate electrode adjacent the head. Thus, the gate length of a semiconductor device, such as a field effect transistor, is reduced while the effective cross-sectional area of the gate electrode is increased whereby the noise characteristics of the semiconductor device are improved.Type: GrantFiled: December 5, 1991Date of Patent: June 15, 1993Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Nobuyuki Kasai, Shinichi Sakamoto, Takuji Sonoda, Tetsuya Yagi
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Patent number: 5185534Abstract: At least two unit transistor groups, each including unit transistors arranged along a straight line, are disposed on a substrate parallel to and facing each other. Each transistor in one group and a facing transistor in the other group have integral first, second, and control electrodes. The first, second, and control electrodes of the unit transistors are connected to associated respective electrode pads.Type: GrantFiled: June 3, 1991Date of Patent: February 9, 1993Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Shinichi Sakamoto, Takuji Sonoda, Nobuyuki Kasai