Abstract: A semiconductor memory includes a DRAM having, as seen in planar view, a first bit line and a second bit line formed on a first active area, a first cell contact formed on the first active area, and a first capacitor contact formed on the first cell contact and which is connected to a capacitor. As seen in planar view, the first cell contact is positioned closer to the second bit line than to the first bit line, and the first capacitor contact is formed offset in a direction approaching the first bit line with respect to the first cell contact.

Abstract: Two interconnect layers are electrically connected while reducing the number of manufacturing steps. A contact plug 9c which is formed into a beaded shape in a layer underlying two interconnects 11C and 11D and which also electrically connects the two interconnects 11C and 11D is included. The two interconnects 11C and 11D are separated to each other and are formed in a same layer. The contact plug 9c is simultaneously formed with a contact plug 9b to be connected to an interconnect 4b and a contact plug 9a to be connected to a source/drain region 6.

Abstract: A semiconductor memory includes a DRAM having, as seen in planar view, a first bit line and a second bit line formed on a first active area, a first cell contact formed on the first active area, and a first capacitor contact formed on the first cell contact and which is connected to a capacitor. As seen in planar view, the first cell contact is positioned closer to the second bit line than to the first bit line, and the first capacitor contact is formed offset in a direction approaching the first bit line with respect to the first cell contact.

Abstract: A lower electrode projects outward from a common end face of an upper electrode and a capacitor film. A protective film, which is made of a different material from the capacitor film, is deposited on top of a part of the lower electrode outside the end face. The protective film also extends to the position at a certain distance inward from the end face, so that it is placed between the capacitor film and the lower electrode. The capacitor film thereby has a stepped surface near the end face due to the presence of the protective film, which suppresses the progress of damage during etching of the upper electrode and the capacitor film. Further, the protective film prevents the occurrence of damage in the lower electrode.

Abstract: The semiconductor device has a fuse and a fuse opening created above the fuse. The fuse is divided into a plurality of lines at a crossing portion where the fuse crosses with an edge of the fuse opening. The plurality of divided lines of the fuse 101 are in parallel with each other and in perpendicular to the edge of the fuse opening.

Abstract: A semiconductor apparatus includes an internal layer where a first power supply line to provide a first power supply to transistors in a layout cell and an internal cell line to connect transistors in the layout cell are placed, an input/output line connected with an input/output terminal of the layout cell is placed, and a shield line which is placed between the internal layer and the input/output line so as to cover the internal layer and the first power supply line.

Abstract: A semiconductor device includes a first inverter, a second inverter, and an inner wiring connecting the inverters, in which the inner wiring forms a capacitor element, and the capacitor element includes an interlayer insulation film having an aperture on a semiconductor substrate, a lower electrode covering a bottom wall and a side wall of the aperture, the bottom wall being the semiconductor substrate and the side wall being a part of the interlayer insulation film, a capacitor insulation film arranged on the lower electrode and a part of the interlayer insulation film, the capacitor insulation film covering corners of the capacitor insulation film, the corners being situated at opposite side of the semiconductor substrate, and an upper electrode on the capacitor insulation film, the upper electrode covering the aperture.

Abstract: A lower electrode projects outward from a common end face of an upper electrode and a capacitor film. A protective film, which is made of a different material from the capacitor film, is deposited on top of a part of the lower electrode outside the end face. The protective film also extends to the position at a certain distance inward from the end face, so that it is placed between the capacitor film and the lower electrode. The capacitor film thereby has a stepped surface near the end face due to the presence of the protective film, which suppresses the progress of damage during etching of the upper electrode and the capacitor film. Further, the protective film prevents the occurrence of damage in the lower electrode.

Abstract: Two interconnect layers are electrically connected while reducing the number of manufacturing steps. A contact plug 9c which is formed into a beaded shape in a layer underlying two interconnects 11C and 11D and which also electrically connects the two interconnects 11C and 11D is included. The two interconnects 11C and 11D are separated to each other and are formed in a same layer. The contact plug 9c is simultaneously formed with a contact plug 9b to be connected to an interconnect 4b and a contact plug 9a to be connected to a source/drain region 6.

Abstract: A semiconductor apparatus includes an internal layer where a first power supply line to provide a first power supply to transistors in a layout cell and an internal cell line to connect transistors in the layout cell are placed, an input/output line connected with an input/output terminal of the layout cell is placed, and a shield line which is placed between the internal layer and the input/output line so as to cover the internal layer and the first power supply line.

Abstract: The semiconductor device includes a reference voltage generator circuit and a circuit different from the reference voltage generator circuit. A semiconductor element of the reference voltage generator circuit has a channel region where a substrate impurity concentration is substantially uniform at least in the vicinity of a drain region. A semiconductor element of the circuit different from the reference voltage generator circuit has a channel region where a substrate impurity concentration is higher than in other part of the region at least in the drain region.

Abstract: The semiconductor device has a fuse and a fuse opening created above the fuse. The fuse is divided into a plurality of lines at a crossing portion where the fuse crosses with an edge of the fuse opening. The plurality of divided lines of the fuse 101 are in parallel with each other and in perpendicular to the edge of the fuse opening.

Abstract: The semiconductor device includes a reference voltage generator circuit and a circuit different from the reference voltage generator circuit. A semiconductor element of the reference voltage generator circuit has a channel region where a substrate impurity concentration is substantially uniform at least in the vicinity of a drain region. A semiconductor element of the circuit different from the reference voltage generator circuit has a channel region where a substrate impurity concentration is higher than in other part of the region at least in the drain region.

Abstract: When a top surface area for a plurality of dummy patterns 13 and a width for a plurality of trenches 12 are set on the basis of a ratio (an occupation density of the film for polishing in an adjacent region 10) of a total top surface area for raised sections of the film for polishing to a horizontally projected area of the adjacent region 10, it is possible to suppress dishing and erosion and thereby attain a high planarity when a film for polishing is formed on a semiconductor substrate, wherein dummy patterns 13 partitioned by a plurality of trenches 12 are disposed in an element isolation region 11, and planarization by the CMP is applied thereto.

Abstract: When a top surface area for a plurality of dummy patterns 13 and a width for a plurality of trenches 12 are set on the basis of a ratio (an occupation density of the film for polishing in an adjacent region 10) of a total top surface area for raised sections of the film for polishing to a horizontally projected area of the adjacent region 10, it is possible to suppress dishing and erosion and thereby attain a high planarity when a film for polishing is formed on a semiconductor substrate, wherein dummy patterns 13 partitioned by a plurality of trenches 12 are disposed in an element isolation region 11, and planarization by the CMP is applied thereto.

Abstract: A heat resistant thermoplastic resin composition comprising (a) 5 to 99% by weight of a poly(phenylene ether), (b) 95 to 1% by weight of a thermoplastic resin which is obtained by polymerizing in the absence of a rubber-like polymer a resin constituent mixture comprising an aromatic alkenyl compound, an alkenyl cyanide compound, and, if necessary, other alkenyl monomers copolymerizable with said monomers, and (c) up to 94% by weight of other styrenic resins, said thermoplastic resin (b) comprising (A) 1-50% by weight of a polymer having an alkenyl cyanide compound content of 1% by weight or more but less than 10% by weight, (B) 1-70% by weight of a polymer having an alkenyl cyanide compound content of 10% by weight or more but less than 20% by weight, (C) 5-90% by weight of a polymer having an alkenyl cyanide compound content of 20% by weight or more but less than 40% by weight, and (D) up to 70% by weight of a polymer having an alkenyl cyanide compound content of 40% by weight or more, and having a total alk