Patents by Inventor Nobuyuki Kawase

Nobuyuki Kawase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190279545
    Abstract: A system of inspecting a display panel includes an inspection apparatus configured to determine whether the display panel has a lighting defect. If determining that the display panel has a lighting defect, the inspection apparatus is configured to make a cleaner to clean a portion of the display panel having the lighting defect. The inspection apparatus is configured to determine presence or absence of the lighting defect again at least on the portion of the display panel having the lighting defect after the cleaning. The inspection apparatus determines that the display panel has no defect if detecting no lighting defect after the cleaning or if determining that pre-cleaning lighting defect information and post-cleaning lighting defect information does not match, and the inspection apparatus determines that the display panel has a defect if determining that the pre-cleaning lighting defect information and the post-cleaning lighting defect information match.
    Type: Application
    Filed: March 6, 2019
    Publication date: September 12, 2019
    Inventors: HIDEKI SHINOBU, NOBUYUKI KAWASE, TERUO KAWAMURA
  • Publication number: 20190146666
    Abstract: A display device includes a display surface displaying information thereon and an outer surface different from the display surface. The outer surface includes a mark providing a sense of touching different from a sense of touching a surrounding portion thereof such that a touching position of the display device is recognized.
    Type: Application
    Filed: November 13, 2018
    Publication date: May 16, 2019
    Inventors: HIDEKI SHINOBU, NOBUYUKI KAWASE
  • Patent number: 9614001
    Abstract: An active matrix substrate includes a plurality of bus lines (1, 2) provided in a pixel region, a plurality of signal terminals (5) provided in a connection terminal region (K), connection lines (3), additional signal terminals (11), test lines (8), and switching elements (4). The switching elements (4) are divided into a plurality of groups, and can control connections between the bus lines and the test lines (8) on a group basis, and connection elements (12) that each include a diode or a switching element and connect the signal terminals (5) to each other are provided in the connection terminal region (K).
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: April 4, 2017
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Nobuyuki Kawase, Isao Ogasawara, Kazuhide Ikuta
  • Publication number: 20130099816
    Abstract: An active matrix substrate includes a plurality of bus lines (1, 2) provided in a pixel region, a plurality of signal terminals (5) provided in a connection terminal region (K), connection lines (3), additional signal terminals (11), test lines (8), and switching elements (4). The switching elements (4) are divided into a plurality of groups, and can control connections between the bus lines and the test lines (8) on a group basis, and connection elements (12) that each include a diode or a switching element and connect the signal terminals (5) to each other are provided in the connection terminal region (K).
    Type: Application
    Filed: June 22, 2011
    Publication date: April 25, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Nobuyuki Kawase, Isao Ogasawara, Kazuhide Ikuta
  • Publication number: 20110298484
    Abstract: An electronic circuit of at least one embodiment of the present invention includes: a plurality of electronic parts, of the plurality of electronic parts, at least one electronic part being at least one main part and the other electronic parts being auxiliary parts, the at least one main part being necessary for determination of whether or not the electronic circuit operates normally, the auxiliary parts being unnecessary for determination of whether or not the electronic circuit operates normally, the auxiliary parts being connected to a line which is connected to the at least one main part so as to supply a signal necessary for operation of the at least one main part or output a signal obtained by the operation of the at least one main part.
    Type: Application
    Filed: November 19, 2009
    Publication date: December 8, 2011
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Nobuyuki Kawase, Isao Ogasawara, Kazuhide Ikuta
  • Patent number: 5825196
    Abstract: Disclosed herein is a method for detecting a defect of an active matrix liquid crystal panel, the method including a step of inputting a data signal for displaying an image having a luminance level lower than a maximum luminance level to a first signal line while inputting a data signal for displaying a black image to a second signal line and a third signal line, the second signal line and the third signal line adjoining the first signal line, thereby causing pixels corresponding to the first signal line to display a single color. According to the method of the present invention, any defective pixel is displayed darker than normal, owing to a decrease in the transmittance, so that point defects such as S-D leak defects can be easily detected.
    Type: Grant
    Filed: October 29, 1996
    Date of Patent: October 20, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Katsumi Irie, Nobuyuki Kawase, Takafumi Hayama, Touko Kasahara
  • Patent number: 5631896
    Abstract: A hitless path switching method without a bit loss. The same digital line signals on a working path and a protection path are continuously monitored independently for bit errors. If a bit error occurs in the working path and no bit error occurs in the protection path, a switching trigger is produced and a switching operation from the working path to the protection path is performed on a data block basis. Only correct data are transferred to downstream apparatuses. Reliable hitless switching is achieved not only in response to a failure in a path, but also in response to a bit error. Using data blocks of one frame length with an indicator for bit error checking placed at its beginning or top makes effective switching possible.
    Type: Grant
    Filed: July 17, 1995
    Date of Patent: May 20, 1997
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Nobuyuki Kawase, Yoshiaki Yamabayashi, Yoshihiko Uematsu
  • Patent number: 5565557
    Abstract: A process for producing a sucrose fatty acid ester wherein the sucrose fatty acid ester is recovered from a reaction mixture prepared by reacting sucrose with a fatty acid alkyl ester in the presence of an alkali catalyst by using dimethyl sulfoxide as a reaction solvent, the process comprising: (i) subjecting the reaction mixture to a first liquid-liquid extraction by using a hardly water-miscible organic solvent, which is selected from an alcohol having at least 4 carbon atoms and a ketone having at least 4 carbon atoms, and water as extractants, with regulating the pH value of an aqueous phase to 3 to 7.
    Type: Grant
    Filed: December 23, 1994
    Date of Patent: October 15, 1996
    Assignee: Mitsubishi Chemical Corporation
    Inventors: Yasuaki Koyama, Nobuyuki Kawase, Hiroshi Yamamoto, Shigetomi Kawata, Yukio Kasori
  • Patent number: 5473261
    Abstract: The inspection apparatus of the invention inspects a display device including first and second bus lines formed on an active matrix substrate. The inspection apparatus includes a first substrate unit and a second substrate unit each having a pair of substrates and connecting films therebetween. On one substrate of each substrate unit, inspection terminals and first inspection lines are formed and each of the inspection lines are connected to one of the inspection terminals. On the other substrate of each substrate unit, second inspection lines are provided. The first and second inspection lines of the substrates are selectively connected by the connecting films. During inspection, the second inspection lines of the first substrate unit are brought directly in contact with the first bus lines, so that each of the first bus lines is connected to one of the inspection terminals of the first substrate unit.
    Type: Grant
    Filed: June 7, 1994
    Date of Patent: December 5, 1995
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hideji Marumoto, Nobuyuki Kawase, Masasi Hosomi, Katsumi Irie, Koji Fukuda, Yuichiro Mochizuki