Abstract: A storage device includes a storage unit, a communication port configured to perform serial communication with an external device, and a controller configured to access the storage unit based on a command communicated from the external device through the communication port, and set the communication port to a power-saving mode before the communication port receives any signal for synchronization.

Abstract: A storage device includes a storage unit, a communication port configured to perform serial communication with an external device, and a controller configured to access the storage unit based on a command communicated from the external device through the communication port, and set the communication port to a power-saving mode before the communication port receives any signal for synchronization.

Abstract: A storage device includes a storage unit, a communication port configured to perform serial communication with an external device, and a controller configured to access the storage unit based on a command communicated from the external device through the communication port, and set the communication port to a power-saving mode before the communication port receives any signal for synchronization.

Abstract: A storage device includes a storage unit, a communication port configured to perform serial communication with an external device, and a controller configured to access the storage unit based on a command communicated from the external device through the communication port, and set the communication port to a power-saving mode before the communication port receives any signal for synchronization.

Abstract: A storage device includes a storage unit, a communication port configured to perform serial communication with an external device, and a controller configured to access the storage unit based on a command communicated from the external device through the communication port, and set the communication port to a power-saving mode before the communication port receives any signal for synchronization.

Abstract: A storage device includes a non-volatile storage, and a controller configured to carry out, in parallel, operations in response to a plurality of commands received from a host and queued in a command queue. When the controller receives, from the host, a read command and then a subsequent command before all data read from the non-volatile storage are transmitted to the host in response to the read command, the controller transmits a response to the subsequent command after part of the data read from the non-volatile storage are transmitted to the host and before the all data read from the non-volatile storage are transmitted to the host.

Abstract: A memory device includes a memory unit, a communication interface through which commands are received from a plurality of hosts, and a controller configured to store the commands in a queue and determine an order of execution of the commands according to when the commands were added to the queue and whether or not the commands issued from a host that is designated as a priority host. The controller determines the commands issued from the priority host to be executed prior to other commands that were not issued from the priority host, and determines the other commands to be executed in the order they were added to the queue.

Abstract: A storage device includes a non-volatile storage, and a controller configured to carry out, in parallel, operations in response to a plurality of commands received from a host and queued in a command queue. When the controller receives, from the host, a read command and then a subsequent command before all data read from the non-volatile storage are transmitted to the host in response to the read command, the controller transmits a response to the subsequent command after part of the data read from the non-volatile storage are transmitted to the host and before the all data read from the non-volatile storage are transmitted to the host.

Abstract: A memory device includes a memory unit, a communication interface through which commands are received from a plurality of hosts, and a controller configured to store the commands in a queue and determine an order of execution of the commands according to when the commands were added to the queue and whether or not the commands issued from a host that is designated as a priority host. The controller determines the commands issued from the priority host to be executed prior to other commands that were not issued from the priority host, and determines the other commands to be executed in the order they were added to the queue.

Abstract: A storage device includes a storage unit, a communication port configured to perform serial communication with an external device, and a controller configured to access the storage unit based on a command communicated from the external device through the communication port, and set the communication port to a power-saving mode before the communication port receives any signal for synchronization.

Abstract: According to one embodiment, a memory system includes a command table that stores therein a write command received from a host, a nonvolatile memory that stores therein write data, and a response setting circuit that creates a management table that corresponds to the write command in the command table. Furthermore, the memory system includes a transport layer that generates the response frame based on the management table and a physical layer that transmits the response frame to the host.

Abstract: According to one embodiment, a data storage device comprises a buffer memory and a controller. The buffer memory stores a data group including sector unit data with addresses specified by a host, the data group in unit of page includes a plurality of addresses. The controller comprises an adding module configured to be operative, if the sector unit data with addresses specified by the host as valid addresses for write targets are stored in the buffer, to add information that identifies a last address included in valid addresses belonging to the same page addresses and specified by the host and starting with a start address, to a single sector unit data with the last address.

Abstract: According to one embodiment, a memory system including plural processing units, each of which is provided for each transmission path, and a data distribution unit, is provided. The data distribution unit distributes a data frame to a write control unit that has execution management information including identification information equal to identification information in the received data frame, in the case where the same address is set to the input/output units in the plural processing units. The data distribution unit transfers the data frame to the write control unit in the processing unit including the input/output unit from which the data frame is received, in the case where a different address is set to the input/output unit in each of the processing units.

Abstract: According to one embodiment, a command management device includes a command buffer, a free address register and a FIFO unit with entries. The command buffer stores commands received from a host. The entries include address sections configured to store addresses of the areas in the command buffer in which the respective commands are stored. The address sections are connected together like a ring. Each of the address sections includes a substitute module configured to substitute either the free address held in the free address register or a second address stored in the address section preceding the each of the address sections for a first address stored in the each of the address sections.

Abstract: According to one embodiment, an interface controller includes a first timer, a monitoring result obtaining module, a monitoring result buffer and an adjuster. The first timer measures elapsed time from a first time point when the interface controller is connected to a first host device of a plurality of host devices and detects a first timeout based on the measured elapsed time and a first timeout value. The monitoring result obtaining module obtains, as a monitoring result, a value indicative of the elapsed time measured at a second time point when a first frame is received from the first host device after the first time point and before the first timeout is detected. The monitoring result buffer stores the monitoring result obtained. The adjuster adjusts the first timeout value based on at least one monitoring result stored in the monitoring result buffer.

Abstract: According to one embodiment, a data hold module is configured to receive first data synchronized with a first clock signal on the basis of a second timing signal and output second data obtained by synchronizing the received first data with a second clock signal differing from the first clock signal in frequency. A reception timing generator is configured to generate a timing signal synchronized with the second clock signal as the second timing signal on the basis of a first timing signal corresponding to the first data and synchronized with the first clock signal. The reception timing generator comprises flip-flops connected in cascade. An update timing adjusting module is configured to limit the timing to update the flip-flops in value on the basis of an update enable signal synchronized with the second clock signal.

Abstract: According to one embodiment, a command management device includes a command buffer, a free address register and a FIFO unit with entries. The command buffer stores commands received from a host. The entries include address sections configured to store addresses of the areas in the command buffer in which the respective commands are stored. The address sections are connected together like a ring. Each of the address sections includes a substitute module configured to substitute either the free address held in the free address register or a second address stored in the address section preceding the each of the address sections for a first address stored in the each of the address sections.

Abstract: According to one embodiment, a data hold module is configured to receive first data synchronized with a first clock signal on the basis of a second timing signal and output second data obtained by synchronizing the received first data with a second clock signal differing from the first clock signal in frequency. A reception timing generator is configured to generate a timing signal synchronized with the second clock signal as the second timing signal on the basis of a first timing signal corresponding to the first data and synchronized with the first clock signal. The reception timing generator comprises flip-flops connected in cascade. An update timing adjusting module is configured to limit the timing to update the flip-flops in value on the basis of an update enable signal synchronized with the second clock signal.

Abstract: A processor includes: a first storage part that stores instructions of a program including sets of instruction groups, which sets are hierarchically structured; a second storage part that stores an address value of the first storage part in which an instruction to be read next is stored; a third storage part that includes storage areas respectively corresponding to hierarchical levels of the program; and a control part that executes, when an instruction read from the first storage part is a call instruction that calls a different one of the sets of instruction groups, a control to store the address value in the second storage part in one of the storage areas of the third storage part that corresponds to one of the hierarchical levels with which the different one of the sets of instruction groups being executed is associated.

Abstract: Information about an attribute of packets that are receivable corresponding to a command is registered. When a packet is received, information about an attribute of the packet received is acquired. Upon occurrence of a reception error that there is no information in the attribute registering unit corresponding to the information acquired by the attribute acquiring unit, a predetermined reception error handling routine is executed according to a type of the reception error.