Patents by Inventor Nobuyuki Nakai
Nobuyuki Nakai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220314753Abstract: The vehicle rear information acquisition system of the disclosure includes: a back window at a rear of a vehicle; and an information acquisition device disposed inside the vehicle, opposing the back window, and configured to apply and/or receive light to acquire information from outside the vehicle, the back window including a glass plate and a coating film on at least a part of a surface of the glass plate, and having a privacy region for protecting privacy inside the vehicle and an information acquisition region opposing the information acquisition device and transmitting the light, the privacy region having the coating film on the surface of the glass plate, the privacy region having a visible light transmittance of 10% or less, the information acquisition region having a visible light transmittance of 25% or more.Type: ApplicationFiled: September 1, 2020Publication date: October 6, 2022Applicant: CENTRAL GLASS COMPANY, LIMITEDInventors: Nobuyuki NAKAI, Takuro KIDOKORO, Mizuki TETSUMURA, Yoshihiko OBARA
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Patent number: 11117830Abstract: A glass article includes a glass substrate, a colored film formed on one of main surfaces of the glass substrate, an uncoated portion where no colored film is formed which is present in part of the one of main surfaces or on an edge face of the glass substrate, a boundary between the colored film and the uncoated portion, and a film thickness varying portion where the colored film gradually tapers in thickness toward the boundary. The uncoated portion is visible in the glass article used as a window, the glass substrate has an absorbance in the wavelength range of 380 nm to 780 nm of 0.10 or lower per mm of thickness, and the glass article has a portion blue in color, gray in color, or pink in color where the colored film is formed.Type: GrantFiled: October 2, 2017Date of Patent: September 14, 2021Assignee: CENTRAL GLASS COMPANY, LIMITEDInventors: Nobuyuki Nakai, Yoshihiko Obara
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Publication number: 20200071226Abstract: A glass article includes a glass substrate, a colored film formed on one of main surfaces of the glass substrate, an uncoated portion where no colored film is formed which is present in part of the one of main surfaces or on an edge face of the glass substrate, a boundary between the colored film and the uncoated portion, and a film thickness varying portion where the colored film gradually tapers in thickness toward the boundary. The uncoated portion is visible in the glass article used as a window, the glass substrate has an absorbance in the wavelength range of 380 nm to 780 nm of 0.10 or lower per mm of thickness, and the glass article has a portion blue in color, gray in color, or pink in color where the colored film is formed.Type: ApplicationFiled: October 2, 2017Publication date: March 5, 2020Applicant: CENTRAL GLASS COMPANY, LIMITEDInventors: Nobuyuki Nakai, Yoshihiko Obara
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Publication number: 20200055772Abstract: A method of producing a colored film-attached glass sheet includes a step of obtaining a colored film-forming coating solution by mixing the following components: (a) a reaction product obtained by reacting an amino group-containing silane compound with at least one boron compound selected from the group consisting of H3BO3 and B2O3; (b) a metal alkoxide and/or a metal alkoxide condensate; (c) a synthetic resin; (d) a triazine-based UV absorber; (e) a solvent substantially consisting of a non-aqueous solvent having an SP value of 8 to 11.5 (cal/cm3)1/2; and (f) a pigment. The colored film-forming coating solution contains the UV absorber in an amount of 5 to 12% by mass relative to the total solids content and the pigment in an amount equal to 0.02 to 0.50 times the amount of the UV absorber by mass ratio.Type: ApplicationFiled: January 24, 2018Publication date: February 20, 2020Applicant: CENTRAL GLASS COMPANY, LIMITEDInventors: Nobuyuki Nakai, Yoshihiko Obara
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Patent number: 10550031Abstract: Disclosed is a glass window having a luminous capability, which is suitable for use in automotive applications, architectural applications, or other applications. Exemplary embodiments of a glass window having a luminous capability include one or more glass sheet layers, a thin film layer having fine particles dispersed in a matrix of a thin film material, and at least one light source for introducing light into the thin film layer. The fine particles scatter the light and generate luminousness of the glass window. Exemplary embodiments of a glass window having luminous capability may further include one or more resinous sheet layers or one or more interlayers such as a plastic film layer.Type: GrantFiled: February 23, 2017Date of Patent: February 4, 2020Assignee: Central Glass Company, LimitedInventors: Michael Bard, Tobias Solchenbach, Yoshihiko Obara, Nobuyuki Nakai
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Publication number: 20190218139Abstract: Disclosed is a glass window having a luminous capability, which is suitable for use in automotive applications, architectural applications, or other applications. Exemplary embodiments of a glass window having a luminous capability include one or more glass sheet layers, a thin film layer having fine particles dispersed in a matrix of a thin film material, and at least one light source for introducing light into the thin film layer. The fine particles scatter the light and generate luminousness of the glass window. Exemplary embodiments of a glass window having luminous capability may further include one or more resinous sheet layers or one or more interlayers such as a plastic film layer.Type: ApplicationFiled: February 23, 2017Publication date: July 18, 2019Inventors: Michael Bard, Tobias Solchenbach, Yoshihiko Obara, Nobuyuki Nakai
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Publication number: 20110083584Abstract: Disclosed is a flaky material formed of an aggregate of fine particles. The aggregate is formed by uniting fine particles to one another. The fine particles are derived from fine particles of an inorganic oxide dispersed in a solvent having an effective (OH?) content of 3×10?5 to 1×10?6 mol/l. The surface of the flaky material has a flatness degree equal to or lower than 0.5 ?m. The flaky material can provide viewers with a high brightness feeling.Type: ApplicationFiled: May 21, 2009Publication date: April 14, 2011Applicant: CENTRAL GLASS COMPANY, LIMITEDInventors: Yukihiro Ougitani, Nobuyuki Nakai, Norikazu Fujiura, Takahisa Kida
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Publication number: 20110026385Abstract: A semiconductor storage device including a memory cell and having a function of refreshing the memory cell, includes a clock generation circuit configured to receive a first clock, generate a second clock based on an inversion of the first clock, and output the second clock. The semiconductor storage device performs operation of the refresh function in synchronization with at least one of the first and second clocks.Type: ApplicationFiled: June 11, 2009Publication date: February 3, 2011Inventors: Nobuyuki Nakai, Hiroyuki Sadakata
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Publication number: 20100315853Abstract: In a semiconductor integrated circuit including a memory macro, such as a DRAM, an SRAM, a ROM, a flash memory, or the like, and a logic circuit, memory macro test-dedicated pads are provided on the memory macro, whereby an increase in the number of normal pads is reduced or prevented to reduce or prevent an increase in the chip area. Moreover, by fixing arrangement (positions) of the pads provided on the memory macro between memory macros of a plurality of memory macro-including semiconductor integrated circuits, a single common probe card for a single chip can be used for the memory macro-including semiconductor integrated circuits, thereby providing low-cost testing.Type: ApplicationFiled: August 23, 2010Publication date: December 16, 2010Applicant: PANASONIC CORPORATIONInventors: Koichiro NOMURA, Shoji Sakamoto, Nobuyuki Nakai
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Patent number: 7536659Abstract: Decreases in area efficiency and wiring efficiency and degradation in performance are prevented which result from imbalances in dimensional ratios between miniaturized control circuits and other components brought by the development of microfabrication process such as a process of fabricating large-capacity DRAMs as hard macros. A memory array region and a control region are placed such that the two regions are in contact with each other and have a convex shape when viewed from above. Because of this, the layout areas of memories such as large-capacity DRAMs are optimized and their production cost can be reduced.Type: GrantFiled: March 7, 2007Date of Patent: May 19, 2009Assignee: Panasonic CorporationInventors: Nobuyuki Nakai, Yuji Yamasaki
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Publication number: 20070214444Abstract: Decreases in area efficiency and wiring efficiency and degradation in performance are prevented which result from imbalances in dimensional ratios between miniaturized control circuits and other components brought by the development of microfabrication process such as a process of fabricating large-capacity DRAMs as hard macros. A memory array region and a control region are placed such that the two regions are in contact with each other and have a convex shape when viewed from above. Because of this, the layout areas of memories such as large-capacity DRAMs are optimized and their production cost can be reduced.Type: ApplicationFiled: March 7, 2007Publication date: September 13, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Nobuyuki NAKAI, Yuji Yamasaki
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Patent number: 7239546Abstract: Only by replacing a conventional fuse element used for a redundant repair of a memory with a CMOS device, since physical processing is not required, there is an advantage on a circuit area in which the upper interconnection can be utilized. However, on a design of a semiconductor device, since the CMOS device requires application of a high voltage for rewriting, there is a problem of being subjected constraint of an arrangement of an interconnection or a semiconductor circuit. For that reason, by arranging the nonvolatile semiconductor memory circuit provided with the nonvolatile memory device which is constituted of a CMOS device between the IO blocks arranged at the periphery of the chip, physical processing due to replacing the conventional fuse element with the CMOS device will not be needed, so that while keeping an advantage on a circuit area that the upper interconnection can be utilized, the problem of the arrangement in consideration of high voltage application can be resolved.Type: GrantFiled: December 13, 2004Date of Patent: July 3, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Nobuyuki Nakai
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Publication number: 20050157570Abstract: Only by replacing a conventional fuse element used for a redundant repair of a memory with a CMOS device, since physical processing is not required, there is an advantage on a circuit area in which the upper interconnection can be utilized. However, on a design of a semiconductor device, since the CMOS device requires application of a high voltage for rewriting, there is a problem of being subjected constraint of an arrangement of an interconnection or a semiconductor circuit. For that reason, by arranging the nonvolatile semiconductor memory circuit provided with the nonvolatile memory device which is constituted of a CMOS device between the IO blocks arranged at the periphery of the chip, physical processing due to replacing the conventional fuse element with the CMOS device will not be needed, so that while keeping an advantage on a circuit area that the upper interconnection can be utilized, the problem of the arrangement in consideration of high voltage application can be resolved.Type: ApplicationFiled: December 13, 2004Publication date: July 21, 2005Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventor: Nobuyuki Nakai
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Patent number: 6879036Abstract: A semiconductor memory device for use in a semiconductor device with a chip on chip structure, which enables a memory specification to be selected and fixed, and improves design and production efficiencies. Bonding bumps corresponding to an input terminal and an output terminal of an interface circuit are connected to bonding bumps provided on another semiconductor device. Then, a polarity of a potential on a bus width varying terminal is fixed by the bonding bump provided on another semiconductor device, so that an isolated input/output specification is selected as a bus specification of the interface circuit and a bus width is selected.Type: GrantFiled: August 22, 2002Date of Patent: April 12, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Nobuyuki Nakai
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Publication number: 20030040140Abstract: A semiconductor memory device for use in a semiconductor device with a chip on chip structure, which enables a memory specification to be selected and fixed, and improves design and production efficiencies. Bonding bumps corresponding to an input terminal and an output terminal of an interface circuit are connected to bonding bumps provided on another semiconductor device. Then, a polarity of a potential on a bus width varying terminal is fixed by the bonding bump provided on another semiconductor device, so that an isolated input/output specification is selected as a bus specification of the interface circuit and a bus width is selected.Type: ApplicationFiled: August 22, 2002Publication date: February 27, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventor: Nobuyuki Nakai
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Patent number: 6074681Abstract: A method of drying konjak slices in producing seasoned dried konjak slices is provided which method allows for reducing the drying time while at the same time drying the konjak slices homogeneously to their deep interior. In manufacturing dried seasoned konjak by drying seasoned konjak to a moisture content of 10 to 30%, the method for drying is characterized by effecting the drying by carrying the seasoned konjak on a heat-resistant netting 1 in an enclosed space 1 and subjecting the seasoned konjak to heated air at a temperature equal to or higher than 60.degree. C. with or without far-infrared radiation irradiation.Type: GrantFiled: February 4, 1999Date of Patent: June 13, 2000Assignee: Sun Foods Co., Ltd.Inventor: Nobuyuki Nakai