Abstract: A method for fast and efficient data downloading in wireless communications. The method includes ways to download file data of a large size from a server (access point) to a user's client (mobile device) at high speed and efficiency by using both mmWave wireless communication and conventional wireless communication (WiFi, 3G, etc.). A server transmits packetized file data to a client. The file data is transmitted as data packets via mmWave. In parallel, the server transmits check packets (roll-call packets) corresponding to the data packets. As a test at the time of establishing links, the latency for each communication line is measured. The receiver side, upon completion of receiving the check packets, checks whether their corresponding mmWave packets have arrived. If any corresponding mmWave packet has not arrived, it is determined that the mmWave packet has been lost and a retransmission request is immediately returned to the server via WiFi.

Abstract: A memory apparatus having a cache memory including cache segments, and memorizing validity data indicative of whether or not each of the sectors contained in each cache segment is a valid sector inclusive of valid data; and a cache controlling component for controlling access to the cache memory. The cache controlling component includes a detecting component for detecting, when writing a cache segment back to the main memory, areas having consecutive invalid sectors by accessing validity data corresponding to the cache segment, and a write-back controlling component issuing a read command to the main memory, the read command being for reading data into each area detected, making the area a valid sector, and writing the data in the cache segment back to the main memory.

Abstract: A method of monitoring signals is disclosed, wherein a plurality of command signals and address signals are consecutively expressed, as a measurement target. The method includes setting a strobe timing that has a predetermined initial value; calculating an error rate by monitoring the plurality of command signals, in accordance with the strobe timing; monitoring the plurality of address signals, and calculating a burst rate from a difference between the consecutive plurality of address signals, in accordance with the strobe timing; identifying timing where the calculated error rate and calculated burst rate are both optimized; and in the event the timing where both the calculated error rate and calculated burst rate are optimized cannot be identified, altering a predetermined value of the set strobe timing, and repeating the calculating, monitoring, and identifying.

Abstract: A method of monitoring signals is disclosed, wherein a plurality of command signals and address signals are consecutively expressed, as a measurement target. The method includes setting a strobe timing that has a predetermined initial value; calculating an error rate by monitoring the plurality of command signals, in accordance with the strobe timing; monitoring the plurality of address signals, and calculating a burst rate from a difference between the consecutive plurality of address signals, in accordance with the strobe timing; identifying timing where the calculated error rate and calculated burst rate are both optimized; and in the event the timing where both the calculated error rate and calculated burst rate are optimized cannot be identified, altering a predetermined value of the set strobe timing, and repeating the calculating, monitoring, and identifying.

Abstract: A method, bus controller, and computer program product for arbitrating use of a communication bus for a certain one of a plurality of interconnected nodes that share the bus. The method includes the steps of: presenting a data frame on the transmitter and receiver side of the bus, where the certain node presents at the transmitter side, where the data frame has a embedded clock of a predetermined timing and a header field, synchronizing, by the certain node, with the embedded clock in the data frame at the receiving side of the bus, successively presenting, by the certain node, an idle pattern on the bus determined by a preassigned node ID, emitting light, by the certain node, on the bus at a predetermined timing preassigned to the certain node, and monitoring light emission on the bus that indicates a bus access request from another one of the nodes.

Abstract: A memory apparatus having a cache memory including cache segments, and memorizing validity data indicative of whether or not each of the sectors contained in each cache segment is a valid sector inclusive of valid data; and a cache controlling component for controlling access to the cache memory. The cache controlling component includes a detecting component for detecting, when writing a cache segment back to the main memory, areas having consecutive invalid sectors by accessing validity data corresponding to the cache segment, and a write-back controlling component issuing a read command to the main memory, the read command being for reading data into each area detected, making the area a valid sector, and writing the data in the cache segment back to the main memory.

Abstract: A method for fast and efficient data downloading in wireless communications. The method includes ways to download file data of a large size from a server (access point) to a user's client (mobile device) at high speed and efficiency by using both mmWave wireless communication and conventional wireless communication (WiFi, 3G, etc.). A server transmits packetized file data to a client. The file data is transmitted as data packets via mmWave. In parallel, the server transmits check packets (roll-call packets) corresponding to the data packets. As a test at the time of establishing links, the latency for each communication line is measured. The receiver side, upon completion of receiving the check packets, checks whether their corresponding mmWave packets have arrived. If any corresponding mmWave packet has not arrived, it is determined that the mmWave packet has been lost and a retransmission request is immediately returned to the server via WiFi.

Abstract: A computer-implemented method, device, and program product for detecting a phase shift between an I data clock and a Q data clock in processing an I data signal or a Q data signal used in quadrature modulation or quadrature demodulation. The method includes: receiving an input of the I data clock and the Q data clock; performing exclusive-ORing (XORing) on the I data clock and the Q data clock; latching a result of the performance of XORing on a phase sampling clock which is asynchronous with the I data clock and the Q data clock; incrementing a first number; incrementing a second number; comparing the incremented first number and the incremented second number and determining, based on a phase determination criterion, a phase shift between the I data clock and the Q data clock; and detecting a phase shift between the I data clock and the Q data clock.

Abstract: An apparatus detects detecting when an extraordinary behavior is performed when a monitoring task is executed on an information processing apparatus. The detecting apparatus includes: an obtaining section for obtaining a measurement data including an executing timing and an execution time for each occasion of execution when the monitoring task is executed for a number of times on the information processing apparatus; a distance calculating section for calculating a distance between a measured point corresponding to each measurement data in a multi-dimensional space on which an executing timing and an execution time are allocated to different coordinates and another measured point placed in a predetermined range; and a determining section for determining whether an extraordinary behavior is performed when the monitoring task corresponding to the measurement data is executed based on the distance obtained for the measured point corresponding to the measurement data.

Abstract: A memory apparatus having a cache memory including cache segments, and memorizing validity data indicative of whether or not each of the sectors contained in each cache segment is a valid sector inclusive of valid data; and a cache controlling component for controlling access to the cache memory. The cache controlling component includes a detecting component for detecting, when writing a cache segment back to the main memory, areas having consecutive invalid sectors by accessing validity data corresponding to the cache segment, and a write-back controlling component issuing a read command to the main memory, the read command being for reading data into each area detected, making the area a valid sector, and writing the data in the cache segment back to the main memory.

Abstract: A method for fast and efficient data downloading in wireless communications. The method includes ways to download file data of a large size from a server (access point) to a user's client (mobile device) at high speed and efficiency by using both mmWave wireless communication and conventional wireless communication (WiFi, 3G, etc.). A server transmits packetized file data to a client. The file data is transmitted as data packets via mmWave. In parallel, the server transmits check packets (roll-call packets) corresponding to the data packets. As a test at the time of establishing links, the latency for each communication line is measured. The receiver side, upon completion of receiving the check packets, checks whether their corresponding mmWave packets have arrived. If any corresponding mmWave packet has not arrived, it is determined that the mmWave packet has been lost and a retransmission request is immediately returned to the server via WiFi.

Abstract: A method, bus controller, and computer program product for arbitrating use of a communication bus for a certain one of a plurality of interconnected nodes that share the bus. The method includes the steps of: presenting a data frame on the transmitter and receiver side of the bus, where the certain node presents at the transmitter side, where the data frame has a embedded clock of a predetermined timing and a header field, synchronizing, by the certain node, with the embedded clock in the data frame at the receiving side of the bus, successively presenting, by the certain node, an idle pattern on the bus determined by a preassigned node ID, emitting light, by the certain node, on the bus at a predetermined timing preassigned to the certain node, and monitoring light emission on the bus that indicates a bus access request from another one of the nodes.

Abstract: A detecting apparatus including a cluster storing unit that stores, for each of clusters into which execution time of previously executed monitored tasks are classified, the range of execution times belonging to the cluster, an acquiring unit that acquires an execution time of the monitored task in response to new execution of the monitored task on the information processing apparatus, and a determining unit that determines the occurrence of an extraordinary behavior during the execution of the monitored task if the execution time of the newly executed monitored task does not fall within any of the ranges corresponding to the clusters.

Abstract: A detecting apparatus detects the degree of correlation between first events and second events repeatedly occurring in an observed apparatus includes an acquiring unit that acquires second event count values each indicating the number of second events occurring during each first period between each first event and the first event next thereto. A measuring unit measures an observed number of each second event count value derived from the number of times the second event count value is observed. A calculating unit calculates the degree of correlation between the first events and the second events based on the observed number of each second event count value.

Abstract: A computer-implemented method, device, and program product for detecting a phase shift between an I data clock and a Q data clock in processing an I data signal or a Q data signal used in quadrature modulation or quadrature demodulation. The method includes: receiving an input of the I data clock and the Q data clock; performing exclusive-ORing (XORing) on the I data clock and the Q data clock; latching a result of the performance of XORing on a phase sampling clock which is asynchronous with the I data clock and the Q data clock; incrementing a first number; incrementing a second number; comparing the incremented first number and the incremented second number and determining, based on a phase determination criterion, a phase shift between the I data clock and the Q data clock; and detecting a phase shift between the I data clock and the Q data clock.

Abstract: An observation apparatus which observers operations of an observation target apparatus, and which includes: an output signal acquisition unit for sequentially acquiring signal values by observing signals outputted by the observation target apparatus; a state storage unit for sequentially storing the acquired signal values; a determination unit for determining whether a first signal value newly acquired is identical with a second signal value which is acquired prior to the first signal value, and which is stored in the state storage unit; and a separation unit for separating and outputting a signal sequence, which includes a plurality of signal values acquired between the first signal value and the second signal value, as transactions of the output signals, on condition that it is determined that the first signal value is identical with the second signal value.

Abstract: An integrated bus architecture for transmitting trace information from a plurality of processors included on an integrated chip having one or more peripheral I/O channels comprises a segmented bus having a plurality of segments arranged in a ring topology and configured to transmit trace information in a circular pathway from upstream segments to downstream segments, and one or more trace output circuits each connected to a respective segment and each including a switch configured to be dynamically toggled between enabled and disabled states. The plurality of segments includes a respective segment for each processor having a coupling unit connected to a trace port of the processor. The coupling unit is configured to receive trace information from the trace port, to receive trace information from the adjacent upstream segment, and to transmit items of trace information to the adjacent downstream segment.

Abstract: An integrated bus architecture for transmitting trace information from a plurality of processors included on an integrated chip having one or more peripheral I/O channels comprises a segmented bus having a plurality of segments arranged in a ring topology and configured to transmit trace information in a circular pathway from upstream segments to downstream segments, and one or more trace output circuits each connected to a respective segment and each including a switch configured to be dynamically toggled between enabled and disabled states. The plurality of segments includes a respective segment for each processor having a coupling unit connected to a trace port of the processor. The coupling unit is configured to receive trace information from the trace port, to receive trace information from the adjacent upstream segment, and to transmit items of trace information to the adjacent downstream segment.

Abstract: A method and apparatus for detecting processor behavior in real time using instruction trace data, in one aspect, identifies one or more call addresses from which a function to be observed is called and establishes one or more end addresses of the function. Said one or more call addresses and said one or more end addresses are stored, and compared with a branch address contained in the instruction trace data to detect start and end of the function dynamically in real time.

Abstract: A memory apparatus having a cache memory including cache segments, and memorizing validity data indicative of whether or not each of the sectors contained in each cache segment is a valid sector inclusive of valid data; and a cache controlling component for controlling access to the cache memory. The cache controlling component includes a detecting component for detecting, when writing a cache segment back to the main memory, areas having consecutive invalid sectors by accessing validity data corresponding to the cache segment, and a write-back controlling component issuing a read command to the main memory, the read command being for reading data into each area detected, making the area a valid sector, and writing the data in the cache segment back to the main memory.