Patents by Inventor Nobuyuki Oikawa
Nobuyuki Oikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10715128Abstract: Provided is a power supply voltage detection circuit that prevents offsetting from occurring due to different voltages being applied for an extended period of time to gates of two transistors that constitute a differential pair in a comparator circuit that compares a comparison voltage that is generated based on a power supply voltage to a reference voltage. This power supply voltage detection circuit has a reference voltage generation circuit, a comparison voltage generation circuit, and a comparator circuit that includes a first transistor and a second transistor that constitute a differential pair and each have a gate to which a same bias voltage is applied, and a third transistor and a fourth transistor that are respectively connected in series to the first and second transistors and have sources to which the reference voltage and the comparison voltage are respectively applied.Type: GrantFiled: February 26, 2019Date of Patent: July 14, 2020Assignee: SEIKO EPSON CORPORATIONInventors: Nobuyuki Oikawa, Toshikazu Kuwano
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Patent number: 10454471Abstract: A power supply switching circuit that selects one power supply potential from among a plurality of power supply potentials. This power supply switching circuit is provided with a transistor QP1 that is connected between an input node N1 and node N2 and has a back gate connected to node N1, a transistor QP2 that is connected between node N2 and output node N3 and has a back gate connected to node N3, a transistor QP3 that is connected between input node N4 and node N5 and has a back gate connected to node N4, a transistor QP4 that is connected between the node N5 and N3 and has a back gate connected to node N3, and a control signal generation unit that sets a group of transistors QP1 and QP2 and a group of transistors QP3 and QP4 to a conduction state and sets the other to a non-conduction state.Type: GrantFiled: March 6, 2017Date of Patent: October 22, 2019Assignee: SEIKO EPSON CORPORATIONInventors: Hiroaki Nomizo, Hiroshi Kiya, Nobuyuki Oikawa
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Publication number: 20190267980Abstract: Provided is a power supply voltage detection circuit that prevents offsetting from occurring due to different voltages being applied for an extended period of time to gates of two transistors that constitute a differential pair in a comparator circuit that compares a comparison voltage that is generated based on a power supply voltage to a reference voltage. This power supply voltage detection circuit has a reference voltage generation circuit, a comparison voltage generation circuit, and a comparator circuit that includes a first transistor and a second transistor that constitute a differential pair and each have a gate to which a same bias voltage is applied, and a third transistor and a fourth transistor that are respectively connected in series to the first and second transistors and have sources to which the reference voltage and the comparison voltage are respectively applied.Type: ApplicationFiled: February 26, 2019Publication date: August 29, 2019Applicant: SEIKO EPSON CORPORATIONInventors: Nobuyuki OIKAWA, Toshikazu KUWANO
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Patent number: 10152937Abstract: This semiconductor device includes a first regulator that stabilizes an input voltage to generate a stabilized voltage; a voltage boosting circuit that boosts the stabilized voltage to generate a boosted voltage; a second regulator that stabilizes the boosted voltage to generate a first power supply voltage; and a third regulator that is connected to the second regulator in parallel, and that stabilizes the boosted voltage to generate a second power supply voltage.Type: GrantFiled: August 21, 2017Date of Patent: December 11, 2018Assignee: SEIKO EPSON CORPORATIONInventors: Sachiyuki Abe, Nobuyuki Oikawa
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Publication number: 20180061342Abstract: This semiconductor device includes a first regulator that stabilizes an input voltage to generate a stabilized voltage; a voltage boosting circuit that boosts the stabilized voltage to generate a boosted voltage; a second regulator that stabilizes the boosted voltage to generate a first power supply voltage; and a third regulator that is connected to the second regulator in parallel, and that stabilizes the boosted voltage to generate a second power supply voltage.Type: ApplicationFiled: August 21, 2017Publication date: March 1, 2018Applicant: SEIKO EPSON CORPORATIONInventors: Sachiyuki ABE, Nobuyuki OIKAWA
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Publication number: 20170279447Abstract: A power supply switching circuit that selects one power supply potential from among a plurality of power supply potentials. This power supply switching circuit is provided with a transistor QP1 that is connected between an input node N1 and node N2 and has a back gate connected to node N1, a transistor QP2 that is connected between node N2 and output node N3 and has a back gate connected to node N3, a transistor QP3 that is connected between input node N4 and node N5 and has a back gate connected to node N4, a transistor QP4 that is connected between the node N5 and N3 and has a back gate connected to node N3, and a control signal generation unit that sets a group of transistors QP1 and QP2 and a group of transistors QP3 and QP4 to a conduction state and sets the other to a non-conduction state.Type: ApplicationFiled: March 6, 2017Publication date: September 28, 2017Applicant: SEIKO EPSON CORPORATIONInventors: Hiroaki NOMIZO, Hiroshi KIYA, Nobuyuki OIKAWA
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Publication number: 20100206802Abstract: Two or more sheets of one or more kinds of thermally weldable synthetic resin mesh, woven fabric, knitted fabric, and non-woven cloth are overlaid, and each of the overlaid sheets is welded together so that a prescribed protuberance of molten resin produced when press-welding along the welded part is formed toward a side of the welded part.Type: ApplicationFiled: August 26, 2008Publication date: August 19, 2010Applicant: NIFCO INC.Inventors: Hiroji Sato, Nobuyuki Oikawa
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Patent number: 7544898Abstract: Providing a method for manufacturing a multilayer wiring board and a touch panel, which does not cause decreasing of yields, reliabilities and productivities even though the materials of each board to be stacked are different, and which manufactures the multilayer wiring board and the touch panel at low cost with high productivities. A multilayer wired board constituting at least part of a electrical circuit board in which a plurality of wired boards are stacked so as to face their wired surfaces each other, wherein: electrical connection parts between the multilayer wired boards are connected through an elastic conductive material part adhered to one of the wired boards; and at least part of a peripheral edge portion of the elastic conductive material part is adhered by a double-sided adhesive material part to seal the plurality of multilayer wired boards.Type: GrantFiled: October 6, 2003Date of Patent: June 9, 2009Assignee: Sony CorporationInventors: Tomio Hirano, Masao Ono, Nobuyuki Oikawa
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Patent number: 7479319Abstract: A glass substrate excellent in strength properties and a glass cutting method are provided. When a glass substrate having predetermined size is to be formed by cutting a glass plate, any crack or chip is not generated on a cut face. Therefore, a pulverized powder is prevented from being generated from this portion. A glass substrate is obtained by cutting at least with laser light radiation so that a surface roughness of cut side faces and of the glass substrate are 50 nm or less and a depth of laser marks and on the cut side faces are 0.06 mm or more.Type: GrantFiled: July 18, 2003Date of Patent: January 20, 2009Assignee: Sony CorporationInventors: Tomio Hirano, Nobuyuki Oikawa, Makio Onodera, Masao Ono, Hideki Sato, Yukihiro Onodera
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Publication number: 20040086688Abstract: A glass substrate excellent in strength properties and a glass cutting method are provided. When a glass substrate having predetermined size is to be formed by cutting a glass plate, any crack or chip is not generated on a cut face. Therefore, a pulverized powder is prevented from being generated from this portion. A glass substrate is obtained by cutting at least with laser light radiation so that a surface roughness of cut side faces and of the glass substrate are 50 nm or less and a depth of laser marks and on the cut side faces are 0.06 mm or more.Type: ApplicationFiled: July 18, 2003Publication date: May 6, 2004Applicant: Sony CorporationInventors: Tomio Hirano, Nobuyuki Oikawa, Makio Onodera, Masao Ono, Hideki Sato, Yukihiro Onodera
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Publication number: 20040074671Abstract: Providing a method for manufacturing a multilayer wiring board and a touch panel, which does not cause decreasing of yields, reliabilities and productivities even though the materials of each board to be stacked are different, and which manufactures the multilayer wiring board and the touch panel at low cost with high productivities. A multilayer wired board constituting at least part of a electrical circuit board in which a plurality of wired boards are stacked so as to face their wired surfaces each other, wherein: electrical connection parts between the multilayer wired boards are connected through an elastic conductive material part adhered to one of the wired boards; and at least part of a peripheral edge portion of the elastic conductive material part is adhered by a double-sided adhesive material part to seal the plurality of multilayer wired boards.Type: ApplicationFiled: October 6, 2003Publication date: April 22, 2004Applicant: Sony CorporationInventors: Tomio Hirano, Masao Ono, Nobuyuki Oikawa