Patents by Inventor Nobuyuki Sako

Nobuyuki Sako has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150333117
    Abstract: One semiconductor device includes lower electrodes arranged in rows along first and second directions parallel to the surface of a semiconductor substrate and extending in a third direction perpendicular to the surface of the substrate, a first support film arranged on the upper end of the lower electrodes and having first openings, a second support film arranged in the middle of the lower electrodes in the third direction, and having second openings aligned in a plane in the same pattern as the first openings, a capacitance insulating film covering the surface of the lower electrodes, and upper electrodes covering the surface of the capacitance insulating film. A portion of each of eight lower electrodes contained in two lower electrode unit groups adjacent in the first direction are collectively positioned inside of the first and second openings. A lower electrode unit group is four lower electrodes adjacent in the second direction.
    Type: Application
    Filed: December 10, 2013
    Publication date: November 19, 2015
    Inventors: Nobuyuki Sako, Eiji Hasunuma, Keisuke Otsuka
  • Patent number: 9147686
    Abstract: A method of forming a semiconductor device includes the following processes. A first interlayer insulating film is formed over a cell transistor and a peripheral transistor. A cell contact hole is formed in the first interlayer insulating film, the cell contact hole reaching the cell transistor. A lower contact plug is formed at a bottom of the cell contact hole. A peripheral contact hole is formed in the first interlayer insulating film, the peripheral contact hole reaching the peripheral transistor. A first peripheral contact plug is simultaneously formed in the peripheral contact hole and an upper contact plug in the cell contact hole, the upper contact plug being disposed on the lower contact plug.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: September 29, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Nobuyuki Sako, Eiji Hasunuma
  • Patent number: 8951914
    Abstract: A device manufacturing method includes: sequentially forming a first sacrificial film, a first support film, a second sacrificial film, and a second support film on a semiconductor substrate; forming a hole to pass through these films; forming a crown-shaped electrode covering an inner surface of the hole and connected to the second support film and the first support film; forming a first opening in the second support film into a first pattern designed such that the connection between the crown-shaped electrode and the second support film is at least partially maintained; removing at least a part of the second sacrificial film through the first opening; forming a second opening in the first support film with use of the first opening; and removing the first sacrificial film through the second opening. This method is able to prevent misalignment of openings between the support films.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: February 10, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Nobuyuki Sako
  • Patent number: 8883601
    Abstract: A semiconductor device has memory cell portions and compensation capacitance portions on a single substrate. The memory cell portion and the compensation capacitance portion have mutually different planar surface areas. The memory cell portion and the compensation capacitance portion include capacitance plate electrodes of the same structure. The capacitance plate electrode has a laminated structure including a boron-doped silicon germanium film and a metal film.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: November 11, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Nobuyuki Sako
  • Patent number: 8797362
    Abstract: Disclosed is a rotary input device including: a rotary operation device; a rotation driving section; a detection section; a force sense presenting section to present a force sense by a combination of at least two of applying the rotary force in a clockwise direction, applying the rotary force in a counterclockwise direction, and stopping applying the rotary force; a display control section; a magnification ratio change instructing section; and a scroll instructing section, wherein the magnification ratio change instructing section instructs enlargement when rotating in one side, and instructs reduction when rotating in the other side; the scroll instructing section instructs on the basis of the depressed position; and the force sense presenting section changes a way of presenting the force sense in order that the operator can perceive a display state pertaining to a display position or a display magnification ratio of the image under display distinguishably.
    Type: Grant
    Filed: April 21, 2010
    Date of Patent: August 5, 2014
    Assignees: Pro-Tech Design Corporation, Fukoku Co., Ltd.
    Inventors: Kenji Nagashima, Hirono Tsubota, Takahiko Suzuki, Nobuyuki Sako, Takeshi Kodaira
  • Publication number: 20140038411
    Abstract: A device manufacturing method includes: sequentially forming a first sacrificial film, a first support film, a second sacrificial film, and a second support film on a semiconductor substrate; forming a hole to pass through these films; forming a crown-shaped electrode covering an inner surface of the hole and connected to the second support film and the first support film; forming a first opening in the second support film into a first pattern designed such that the connection between the crown-shaped electrode and the second support film is at least partially maintained; removing at least a part of the second sacrificial film through the first opening; forming a second opening in the first support film with use of the first opening; and removing the first sacrificial film through the second opening. This method is able to prevent misalignment of openings between the support films.
    Type: Application
    Filed: October 4, 2013
    Publication date: February 6, 2014
    Applicant: Elpida Memory, Inc.
    Inventor: Nobuyuki SAKO
  • Patent number: 8637376
    Abstract: To reduce dent defects formed in interlayer CMP process on a capacitor array after forming an interlayer insulating film on the capacitor array thicker than the height of a capacitor, the interlayer insulating film on the capacitor array is subjected to a step height reduction etching to form an opening with etching depth Hd, while remaining a first region that is a distance Lr in a horizontal direction from a rising point of a projected portion of the interlayer insulating film periphery to the capacitor array onto a part of the capacitor array, wherein an aspect ratio (Hd/Lr) of the Hd to the Lr is equal to or less than 0.6.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: January 28, 2014
    Inventors: Shigeru Sugioka, Nobuyuki Sako, Ryoichi Tanabe
  • Publication number: 20130344674
    Abstract: A semiconductor device has memory cell portions and compensation capacitance portions on a single substrate. The memory cell portion and the compensation capacitance portion have mutually different planar surface areas. The memory cell portion and the compensation capacitance portion include capacitance plate electrodes of the same structure. The capacitance plate electrode has a laminated structure including a boron-doped silicon germanium film and a metal film.
    Type: Application
    Filed: August 23, 2013
    Publication date: December 26, 2013
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Nobuyuki SAKO
  • Patent number: 8580681
    Abstract: A device manufacturing method includes: sequentially forming a first sacrificial film, a first support film, a second sacrificial film, and a second support film on a semiconductor substrate; forming a hole to pass through these films; forming a crown-shaped electrode covering an inner surface of the hole and connected to the second support film and the first support film; forming a first opening in the second support film into a first pattern designed such that the connection between the crown-shaped electrode and the second support film is at least partially maintained; removing at least a part of the second sacrificial film through the first opening; forming a second opening in the first support film with use of the first opening; and removing the first sacrificial film through the second opening. This method is able to prevent misalignment of openings between the support films.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: November 12, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Nobuyuki Sako
  • Patent number: 8546232
    Abstract: A semiconductor device has memory cell portions and compensation capacitance portions on a single substrate. The memory cell portion and the compensation capacitance portion have mutually different planar surface areas. The memory cell portion and the compensation capacitance portion include capacitance plate electrodes of the same structure. The capacitance plate electrode has a laminated structure including a boron-doped silicon germanium film and a metal film.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: October 1, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Nobuyuki Sako
  • Publication number: 20130052785
    Abstract: To reduce dent defects formed in interlayer CMP process on a capacitor array after forming an interlayer insulating film on the capacitor array thicker than the height of a capacitor, the interlayer insulating film on the capacitor array is subjected to a step height reduction etching to form an opening having open end shape in which open end length is elongated compared with an opening having linear open end shape.
    Type: Application
    Filed: October 28, 2011
    Publication date: February 28, 2013
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Tatsuya MASHIKO, Shigeru SUGIOKA, Nobuyuki SAKO, Ryoichi TANABE
  • Publication number: 20130052784
    Abstract: To reduce dent defects formed in interlayer CMP process on a capacitor array after forming an interlayer insulating film on the capacitor array thicker than the height of a capacitor, the interlayer insulating film on the capacitor array is subjected to a step height reduction etching to form an opening with etching depth Hd, while remaining a first region that is a distance Lr in a horizontal direction from a rising point of a projected portion of the interlayer insulating film periphery to the capacitor array onto a part of the capacitor array, wherein an aspect ratio (Hd/Lr) of the Hd to the Lr is equal to or less than 0.6.
    Type: Application
    Filed: October 28, 2011
    Publication date: February 28, 2013
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Shigeru SUGIOKA, Nobuyuki SAKO, Ryoichi TANABE
  • Publication number: 20130029487
    Abstract: A device manufacturing method includes: sequentially forming a first sacrificial film, a first support film, a second sacrificial film, and a second support film on a semiconductor substrate; forming a hole to pass through these films; forming a crown-shaped electrode covering an inner surface of the hole and connected to the second support film and the first support film; forming a first opening in the second support film into a first pattern designed such that the connection between the crown-shaped electrode and the second support film is at least partially maintained; removing at least a part of the second sacrificial film through the first opening; forming a second opening in the first support film with use of the first opening; and removing the first sacrificial film through the second opening. This method is able to prevent misalignment of openings between the support films.
    Type: Application
    Filed: July 20, 2012
    Publication date: January 31, 2013
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Nobuyuki SAKO
  • Publication number: 20130029470
    Abstract: A method of forming a semiconductor device includes the following processes. A dummy insulating film is formed over a semiconductor substrate by using a source material that is free of carbon as an essential component. A hole that penetrates the dummy insulating film is formed. A conductive film is formed, which covers at least a side wall of the hole of the dummy insulating film. The dummy insulating film is removed to expose an outer surface of the conductive film.
    Type: Application
    Filed: October 24, 2011
    Publication date: January 31, 2013
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Nana HATAYA, Nobuyuki SAKO, Hiroki YAMAWAKI, Shun FUJIMOTO, Jiro MIYAHARA
  • Publication number: 20130011988
    Abstract: A semiconductor device has memory cell portions and compensation capacitance portions on a single substrate. The memory cell portion and the compensation capacitance portion have mutually different planar surface areas. The memory cell portion and the compensation capacitance portion include capacitance plate electrodes of the same structure. The capacitance plate electrode has a laminated structure including a boron-doped silicon germanium film and a metal film.
    Type: Application
    Filed: June 26, 2012
    Publication date: January 10, 2013
    Applicant: Elpida Memory, Inc.
    Inventor: Nobuyuki SAKO
  • Publication number: 20120100678
    Abstract: A method of forming a semiconductor device includes the following processes. A first interlayer insulating film is formed over a cell transistor and a peripheral transistor. A cell contact hole is formed in the first interlayer insulating film, the cell contact hole reaching the cell transistor. A lower contact plug is formed at a bottom of the cell contact hole. A peripheral contact hole is formed in the first interlayer insulating film, the peripheral contact hole reaching the peripheral transistor. A first peripheral contact plug is simultaneously formed in the peripheral contact hole and an upper contact plug in the cell contact hole, the upper contact plug being disposed on the lower contact plug.
    Type: Application
    Filed: October 12, 2011
    Publication date: April 26, 2012
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Nobuyuki SAKO, Eiji HASUNUMA
  • Publication number: 20110189828
    Abstract: A silicon layer is formed on a silicon substrate by an epitaxial growth, and, then a surface of the silicon layer is oxidized. The surface of the silicon layer is cleaned, to remove foreign material generated on the surface of the silicon layer during the epitaxial growth.
    Type: Application
    Filed: December 13, 2010
    Publication date: August 4, 2011
    Applicant: Elpida Memory, Inc.
    Inventors: Nobuyuki Sako, Eiji Hasunuma, Yuki Togashi
  • Publication number: 20100271343
    Abstract: Disclosed is a rotary input device, including: a rotary operation device; a storage section to store screen information correlated to a display order; a display control section for displaying the screen and selection items; an item switch instructing section to switch the selection item; and a screen switch instructing section to switch the displayed screen, wherein the selection item is switched in a predetermined selection order when the rotary operation device rotates in one direction and switched in a reverse order when the rotary operation device rotates in the other direction, and the first screen is switched to the second screen when the rotary operation device rotates in the one direction in a state in which a last first selection item is selected and switched to the first screen when the device rotates in the other direction in the state in which a top second selection item is selected.
    Type: Application
    Filed: April 21, 2010
    Publication date: October 28, 2010
    Applicants: Funai Electric Co., Ltd., PRO-TECH DESIGN CORPORATION
    Inventors: Kenji Nagashima, Hirono Tsubota, Takahiko Suzuki, Nobuyuki Sako, Takeshi Kodaira
  • Publication number: 20100271402
    Abstract: Disclosed is a rotary input device including: a rotary operation device; a rotation driving section; a detection section; a force sense presenting section to present a force sense by a combination of at least two of applying the rotary force in a clockwise direction, applying the rotary force in a counterclockwise direction, and stopping applying the rotary force; a display control section; a magnification ratio change instructing section; and a scroll instructing section, wherein the magnification ratio change instructing section instructs enlargement when rotating in one side, and instructs reduction when rotating in the other side; the scroll instructing section instructs on the basis of the depressed position; and the force sense presenting section changes a way of presenting the force sense in order that the operator can perceive a display state pertaining to a display position or a display magnification ratio of the image under display distinguishably.
    Type: Application
    Filed: April 21, 2010
    Publication date: October 28, 2010
    Applicants: Funai Electric Co., Ltd., PRO-TECH DESIGN CORPORATION
    Inventors: Kenji NAGASHIMA, Hirono Tsubota, Takahiko Suzuki, Nobuyuki Sako, Takeshi Kodaira
  • Publication number: 20100271344
    Abstract: Disclosed is a rotary input device, including: a rotary operation device rotatable around an axis by receiving a rotation operation of an operator; a rotation driving section to apply a rotary force to the rotary operation device; a pressure detecting section to detect a pressure in an axial direction to the rotary operation device; and a force sense presenting section to present a force sense to the operator operating the rotary operation device by applying a rotary force to the rotary operation device by the rotation driving section when the pressure detecting section detects a predetermined pressure in the axial direction to the rotary operation device.
    Type: Application
    Filed: April 21, 2010
    Publication date: October 28, 2010
    Applicants: Funai Electric Co., Ltd., PRO-TECH DESIGN CORPORATION
    Inventors: Kenji Nagashima, Kazuhiro Takahashi, Takahiko Suzuki, Nobuyuki Sako, Takeshi Kodaira