Patents by Inventor Nobuyuki Sekikawa
Nobuyuki Sekikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9291216Abstract: The electromagnetic clutch (X) includes a rotating shaft (1): a magnetic pole body (2) and a rotor (3) disposed to face each other along an axial direction of the rotating shaft (1); and an armature (4) capable of moving in a direction attachable to or detachable from the rotor (3) along the axial direction of the rotating shaft and forming a magnetic circuit with the magnetic pole body and the rotor. The armature is moved in the axial direction of the rotating shaft by electromagnetic suction force to press the rotor when an exciting coil (21) is in an excitation state. The rotating shaft is configured by an input side shaft portion (11) which is a non-magnetic body and formed of a material having enough strength to support rotation of the rotor and the armature; and an output side shaft portion (12) which is a magnetic body.Type: GrantFiled: April 2, 2012Date of Patent: March 22, 2016Assignee: SINFONIA TECHNOLOGY CO., LTD.Inventors: Ryutaro Nakano, Nobuyuki Sekikawa, Hiromi Okubayashi
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Publication number: 20140021003Abstract: The electromagnetic clutch (X) includes a rotating shaft (1): a magnetic pole body (2) and a rotor (3) disposed to face each other along an axial direction of the rotating shaft (1); and an armature (4) capable of moving in a direction attachable to or detachable from the rotor (3) along the axial direction of the rotating shaft and Ruining a magnetic circuit with the magnetic pole body and the rotor. The armature is moved in the axial direction of the rotating shaft by electromagnetic suction force to press the rotor when an exciting coil (21) is in an excitation state. The rotating shaft is configured by an input side shaft portion (11) which is a non-magnetic body and formed of a material having enough strength to support rotation of the rotor and the armature; and an output side shaft portion (12) which is a magnetic body.Type: ApplicationFiled: April 2, 2012Publication date: January 23, 2014Applicant: SINFONIA TECHNOLOGY CO., LTD.Inventors: Ryutaro Nakano, Nobuyuki Sekikawa, Hiromi Okubayashi
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Patent number: 7125787Abstract: A gate electrode includes a first polysilicon film remaining on a first oxide film, a part of a second polysilicon layer 8 superimposed on the polysilicon layer, and a part of the second polysilicon layer partially extending over second gate oxide films. Thus, the thickness of the gate electrode on the first gate oxide film is the same as that of the gate electrode of the prior art, but the film thickness t2 of the gate electrode 10 on the second gate oxide films 6A and 6B is thinner than the thickness t1 of the prior art. Therefore, the height gap h2 between the gate electrode 10 and the N+type source layer 11 and the height gap h2 between the gate electrode 10 and the N+type drain layer 12 become smaller compared to those of prior art, leading to the improved flatness of the interlayer oxide film 13.Type: GrantFiled: November 25, 2003Date of Patent: October 24, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Nobuyuki Sekikawa, Masaaki Momen, Wataru Andoh, Koichi Hirata
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Patent number: 6858489Abstract: This invention is directed to the reduction of voltage dependence and thus allows easy design of integrated semiconductor circuits. The device is equipped with a P? type resistance layer, in which a first voltage is applied to one end and a second voltage is applied to the other end and which is formed on the surface of an N-well region on the semiconductor substrate, a thin oxide film on the resistance layer, and a resistance bias electrode which includes the silicon layer formed on the thin oxide film. By adjusting the voltage applied to the resistance bias electrode, the voltage dependence of the resistance of the resistance layer is reduced.Type: GrantFiled: September 8, 2003Date of Patent: February 22, 2005Assignee: Sanyo Electric Co., Ltd.Inventors: Nobuyuki Sekikawa, Koichi Hirata, Masaaki Momen, Shinya Enomoto
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Publication number: 20040113208Abstract: A gate electrode includes a first polysilicon film remaining on a first oxide film, a part of a second polysilicon layer 8 superimposed on the polysilicon layer, and a part of the second polysilicon layer partially extending over second gate oxide films. Thus, the thickness of the gate electrode on the first gate oxide film is the same as that of the gate electrode of the prior art, but the film thickness t2 of the gate electrode 10 on the second gate oxide films 6A and 6B is thinner than the thickness t1 of the prior art. Therefore, the height gap h2 between the gate electrode 10 and the N+ type source layer 11 and the height gap h2 between the gate electrode 10 and the N+ type drain layer 12 become smaller compared to those of prior art, leading to the improved flatness of the interlayer oxide film 13.Type: ApplicationFiled: November 25, 2003Publication date: June 17, 2004Applicant: Sanyo Electric Co., Ltd.Inventors: Nobuyuki Sekikawa, Masaaki Momen, Wataru Andoh, Koichi Hirata
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Publication number: 20040048434Abstract: This invention is directed to the reduction of voltage dependence and thus allows easy design of integrated semiconductor circuits. The device is equipped with a P− type resistance layer, in which a first voltage is applied to one end and a second voltage is applied to the other end and which is formed on the surface of an N-well region on the semiconductor substrate, a thin oxide film on the resistance layer, and a resistance bias electrode which includes the silicon layer formed on the thin oxide film. By adjusting the voltage applied to the resistance bias electrode, the voltage dependence of the resistance of the resistance layer is reduced.Type: ApplicationFiled: September 8, 2003Publication date: March 11, 2004Applicant: Sanyo Electric Co. Ltd.Inventors: Nobuyuki Sekikawa, Koichi Hirata, Masaaki Momen, Shinya Enomoto
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Patent number: 6693341Abstract: When an element isolation film is formed by the LOCOS technique, as an underlying buffer layer of an oxidation resisting film, a pad oxidation film and pad poly-Si film are used. When an element is formed, they are used as a gate oxide film and a part of a gate electrode to relax a level difference between the gate electrode and the wiring on the element isolation film. A first poly-Si film (pad poly-Si film) is etched to leave its certain thickness to relax the level difference more greatly. In such a process, in manufacturing a semiconductor integrated circuit using the LOCOS technique, the number of manufacturing steps can be reduced and the level difference between the gate electrode on the gate insulating film and the wiring on the element isolation film can be relaxed.Type: GrantFiled: November 7, 2002Date of Patent: February 17, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Nobuyuki Sekikawa, Wataru Andoh, Masaaki Anezaki, Masaaki Momen
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Patent number: 6690070Abstract: A gate electrode includes a first polysilicon film remaining on a first oxide film, a part of a second polysilicon layer 8 superimposed on the polysilicon layer, and a part of the second polysilicon layer partially extending over second gate oxide films. Thus, the thickness of the gate electrode on the first gate oxide film is the same as that of the gate electrode of the prior art, but the film thickness t2 of the gate electrode 10 on the second gate oxide films 6A and 6B is thinner than the thickness t1 of the prior art. Therefore, the height gap h2 between the gate electrode 10 and the N + type source layer 11 and the height gap h2 between the gate electrode 10 and the N + type drain layer 12 become smaller compared to those of prior art, leading to the improved flatness of the interlayer oxide film 13.Type: GrantFiled: August 10, 2001Date of Patent: February 10, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Nobuyuki Sekikawa, Masaaki Momen, Wataru Andoh, Koichi Hirata
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Patent number: 6670236Abstract: To shorten the production process of the semiconductor device having the capacitance element. The pad oxide film (2) and the first polycrystalline silicon layer (3) are used as a stress buffering material at the time of formation of the element separation oxide film. These are not removed and used as the capacitance insulation film and a portion of the upper electrode of the capacitance element. Thereby, the removing process of the pad•polycrystalline silicon layer, and the dummy oxidation and its removing process in the conventional example, can be omitted and the process can be shortened. Further, a problem of the impurity enhanced oxidation at the time of formation of the capacitance insulation film can be solved.Type: GrantFiled: August 7, 2001Date of Patent: December 30, 2003Assignee: Sanyo Electric Co., Ltd.Inventors: Nobuyuki Sekikawa, Koichi Hirata, Wataru Andoh, Noriyasu Katagiri
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Publication number: 20030062587Abstract: When an element isolation film is formed by the LOCOS technique, as an underlying buffer layer of an oxidation resisting film, a pad oxidation film and pad poly-Si film are used. When an element is formed, they are used as a gate oxide film and a part of a gate electrode to relax a level difference between the gate electrode and the wiring on the element isolation film. A first poly-Si film (pad poly-Si film) is etched to leave its certain thickness to relax the level difference more greatly. In such a process, in manufacturing a semiconductor integrated circuit using the LOCOS technique, the number of manufacturing steps can be reduced and the level difference between the gate electrode on the gate insulating film and the wiring on the element isolation film can be relaxed.Type: ApplicationFiled: November 7, 2002Publication date: April 3, 2003Applicant: Sanyo Electric Co., Ltd., a Japan corporationInventors: Nobuyuki Sekikawa, Wataru Andoh, Masaaki Anezaki, Masaaki Momen
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Patent number: 6489661Abstract: When an element isolation film is formed by the LOCOS technique, as an underlying buffer layer of an oxidation resisting film, a pad oxidation film and pad poly-Si film are used. When an element is formed, they are used as a gate oxide film and a part of a gate electrode to relax a level difference between the gate electrode and the wiring on the element isolation film. A first poly-Si film (pad poly-Si film) is etched to leave its certain thickness to relax the level difference more greatly. In such a process, in manufacturing a semiconductor integrated circuit using the LOCOS technique, the number of manufacturing steps can be reduced and the level difference between the gate electrode on the gate insulating film and the wiring on the element isolation film can be relaxed.Type: GrantFiled: February 15, 2001Date of Patent: December 3, 2002Assignee: Sanyo Electric Co., Ltd.Inventors: Nobuyuki Sekikawa, Wataru Andoh, Masaaki Anezaki, Masaaki Momen
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Publication number: 20020048871Abstract: This invention is directed to the reduction of voltage dependence and thus allows easy design of integrated semiconductor circuits. The device is equipped with a P−type resistance layer, in which a first voltage is applied to one end and a second voltage is applied to the other end and which is formed on the surface of an N-well region on the semiconductor substrate, a thin oxide film on the resistance layer, and a resistance bias electrode which includes the silicon layer formed on the thin oxide film. By adjusting the voltage applied to the resistance bias electrode, the voltage dependence of the resistance of the resistance layer is reduced.Type: ApplicationFiled: October 19, 2001Publication date: April 25, 2002Inventors: Nobuyuki Sekikawa, Koichi Hirata, Masaaki Momen, Shinya Enomoto
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Publication number: 20020041005Abstract: To shorten the production process of the semiconductor device having the capacitance element. The pad oxide film (2) and the first polycrystalline silicon layer (3) are used as a stress buffering material at the time of formation of the element separation oxide film. These are not removed and used as the capacitance insulation film and a portion of the upper electrode of the capacitance element. Thereby, the removing process of the pad• polycrystalline silicon layer, and the dummy oxidation and its removing process in the conventional example, can be omitted and the process can be shortened. Further, a problem of the impurity enhanced oxidation at the time of formation of the capacitance insulation film can be solved.Type: ApplicationFiled: August 7, 2001Publication date: April 11, 2002Applicant: Sanyo Electric Co., Ltd., a Japan corporationInventors: Nobuyuki Sekikawa, Koichi Hirata, Wataru Andoh, Noriyasu Katagiri
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Publication number: 20020038895Abstract: A gate electrode includes a first polysilicon film remaining on a first oxide film, a part of a second polysilicon layer 8 superimposed on the polysilicon layer, and a part of the second polysilicon layer partially extending over second gate oxide films. Thus, the thickness of the gate electrode on the first gate oxide film is the same as that of the gate electrode of the prior art, but the film thickness t2 of the gate electrode 10 on the second gate oxide films 6A and 6B is thinner than the thickness t1 of the prior art. Therefore, the height gap h2 between the gate electrode 10 and the N + type source layer 11 and the height gap h2 between the gate electrode 10 and the N + type drain layer 12 become smaller compared to those of prior art, leading to the improved flatness of the interlayer oxide film 13.Type: ApplicationFiled: August 10, 2001Publication date: April 4, 2002Inventors: Nobuyuki Sekikawa, Masaaki Momen, Wataru Andoh, Koichi Hirata
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Patent number: 6307251Abstract: To shorten the production process of the semiconductor device having the capacitance element. The pad oxide film (2) and the first polycrystalline silicon layer (3) are used as a stress buffering material at the time of formation of the element separation oxide film. These are not removed and used as the capacitance insulation film and a portion of the upper electrode of the capacitance element. Thereby, the removing process of the pad.polycrystalline silicon layer, and the dummy oxidation and its removing process in the conventional example, can be omitted and the process can be shortened. Further, a problem of the impurity enhanced oxidation at the time of formation of the capacitance insulation film can be solved.Type: GrantFiled: November 22, 1999Date of Patent: October 23, 2001Assignee: Sanyo Electric Co., Ltd.Inventors: Nobuyuki Sekikawa, Koichi Hirata, Wataru Andoh, Noriyasu Katagiri
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Publication number: 20010029093Abstract: When an element isolation film is formed by the LOCOS technique, as-an underlying buffer layer of an oxidation resisting film, a pad oxidation film and pad poly-Si film are used. When an element is formed, they are used as a gate oxide film and a part of a gate electrode to relax a level difference between the gate electrode and the wiring on the element isolation film. A first poly-Si film (pad poly-Si film) is etched to leave its certain thickness to relax the level difference more greatly. In such a process, in manufacturing a semiconductor integrated circuit using the LOCOS technique, the number of manufacturing steps can be reduced and the level difference between the gate electrode on the gate insulating film and the wiring on the element isolation film can be relaxed.Type: ApplicationFiled: February 15, 2001Publication date: October 11, 2001Applicant: Sanyo Electric Co., Ltd., a Japan CorporationInventors: Nobuyuki Sekikawa, Wataru Andoh, Masaaki Anezaki, Masaaki Momen
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Patent number: 6211046Abstract: When an element isolation film is formed by the LOCOS technique, as an underlying buffer layer of an oxidation resisting film, a pad oxidation film and pad poly-Si film are used. When an element is formed, they are used as a gate oxide film and a part of a gate electrode to relax a level difference between the gate electrode and the wiring on the element isolation film. A first poly-Si film (pad poly-Si film) is etched to leave its certain thickness to relax the level difference more greatly. In such a process, in manufacturing a semiconductor integrated circuit using the LOCOS technique, the number of manufacturing steps can be reduced and the level difference between the gate electrode on the gate insulating film and the wiring on the element isolation film can be relaxed.Type: GrantFiled: July 27, 1999Date of Patent: April 3, 2001Assignee: Sanyo Electric Co., Ltd.Inventors: Nobuyuki Sekikawa, Wataru Andoh, Masaaki Anezaki, Masaaki Momen
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Patent number: 5193278Abstract: Apparatus for cutting foliage having a rotating head and an annular ring mounted for independent rotation in the head. A cam follower is pivotally mounted in the ring and is guided along a circumferential camming surface formed in the head. The camming surface has spaced apart lobes located adjacent to stops. The free end of a supply line is passed over the cam follower and passed out of the ring to a predetermined cutting length. When the head is rotating at operational speed, the resultant centrifugal force of the follower and the line will hold the follower against the stop. If the line is worn or damaged the holding force is decreased and the follower is released and guided over the stop thus allowing the ring to turn relative to the head until the next stop is encountered. This causes a given amount of line to be played out to replenish the damaged or worn section.Type: GrantFiled: April 2, 1992Date of Patent: March 16, 1993Assignee: Starting Industry Company LimitedInventors: Mitsuo Osakabe, Minoru Shibasaki, Toshimichi Kaneniwa, Nobuyuki Sekikawa
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Patent number: 5141881Abstract: A method of making a semiconductor integrated circuit provided with an isolating region constituted of an upper and lower isolating regions, and integrated circuit element regions is disclosed, wherein: the lower isolating region is diffused upward to a depth of a little more than half the thickness of an epitaxial layer to link with the upper isolating region prior to a doping of the upper isolating region; the doping of the lower isolating region and integrated circuit element regions, is implemented by means of ion implantation through a resist film which is capable of blocking ions implanted and in which specified doping windows have been formed in advance, and a SiO.sub.2 film is used as a reference mask in an ion implanting step, and the respective borders of the upper isolating region and the specified regions of the circuit elements is determined by self-alignment.Type: GrantFiled: April 18, 1990Date of Patent: August 25, 1992Assignee: Sanyo Electric Co., Ltd.Inventors: Kazuo Takeda, Toshimasa Sadakata, Teruo Tabata, Nobuyuki Sekikawa, Tadayoshi Takada, Yasuhiro Tamada, Yoshiaki Sano
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Patent number: 5023195Abstract: After a base region and a base contact region, a diffused resistance region and a pair of contact regions formed at each end of the diffused resistance region are formed, an silicon oxide film of essentially uniform thickness is formed anew on the surface of an epitaxial layer. In the silicon oxide film, a collector contact/doping window, a base contact window, an emitter contact/doping window, a lower layer electrode contact window, and a diffused resistance element contact window are formed simultaneously, then the base contact region and the diffused resistance element contact regions are shielded by a mask and a collector contact region, an emitter contact region, and a lower layer electrode contact region are doped. The method of manufacturing a semiconductor integrated circuit of the present invention has the advantages that all insulating films have a uniform film thickness, eliminates the problems of side etching when the contact windows or dopant windows are formed or of etching the element regions.Type: GrantFiled: May 16, 1990Date of Patent: June 11, 1991Assignee: Sanyo Electric Co., Ltd.Inventors: Nobuyuki Sekikawa, Tadayoshi Takada