Abstract: An encryption circuit includes a fundamental vector generation circuit configured to generate a random number sequence for serving as a fundamental vector based on an initial vector, an image mask generation circuit configured to generate an image mask with a mask value set for each pixel in a region to be encrypted smaller than a frame size of the image, based on the fundamental vector and coordinate information for specifying the region to be encrypted, and an XOR operation circuit configured to compute an exclusive OR between each mask value of the image mask and each pixel value of the image data to generate encrypted image data.

Abstract: In an earliest vertical synchronization period after sending an encoded image data is restarted, a first reference image determination circuit determines to employ a local decoded image generated in a vertical synchronization period immediately preceding a vertical synchronization period in which an error occurs among multiple local decoded images stored in a first DRAM as a reference image. In an earliest vertical synchronization period after a decoding circuit is reset, a second reference image determination circuit determines to employ a decoded image generated in the vertical synchronization period immediately preceding the vertical synchronization period in which the error occurs among multiple decoded images stored in a second DRAM as a reference image.

Abstract: An encryption circuit includes a fundamental vector generation circuit configured to generate a random number sequence for serving as a fundamental vector based on an initial vector, an image mask generation circuit configured to generate an image mask with a mask value set for each pixel in a region to be encrypted smaller than a frame size of the image, based on the fundamental vector and coordinate information for specifying the region to be encrypted, and an XOR operation circuit configured to compute an exclusive OR between each mask value of the image mask and each pixel value of the image data to generate encrypted image data.

Abstract: If the number of frames in a GOP of an input stream is not less than 15, the GOP is determined as a control unit time. If the number of frames in the GOP is less than 15, the following GOP is connected thereto until the number of frames becomes not less than 15 and the connected GOPs are determined as a control unit time. After correcting the control unit time, the average input bit rate Sn in each control unit time is obtained, and by using information on the input stream including the average input bit rate Sn, a quantization step value of an output stream is calculated.

Abstract: In an earliest vertical synchronization period after sending an encoded image data is restarted, a first reference image determination circuit determines to employ a local decoded image generated in a vertical synchronization period immediately preceding a vertical synchronization period in which an error occurs among multiple local decoded images stored in a first DRAM as a reference image. In an earliest vertical synchronization period after a decoding circuit is reset, a second reference image determination circuit determines to employ a decoded image generated in the vertical synchronization period immediately preceding the vertical synchronization period in which the error occurs among multiple decoded images stored in a second DRAM as a reference image.

Abstract: In an earliest vertical synchronization period after sending an encoded image data is restarted, a first reference image determination circuit determines to employ a local decoded image generated in a vertical synchronization period immediately preceding a vertical synchronization period in which an error occurs among multiple local decoded images stored in a first DRAM as a reference image. In an earliest vertical synchronization period after a decoding circuit is reset, a second reference image determination circuit determines to employ a decoded image generated in the vertical synchronization period immediately preceding the vertical synchronization period in which the error occurs among multiple decoded images stored in a second DRAM as a reference image.

Abstract: The image processor includes a ? multiplier circuit that approximately multiplies an input value X by ?. The ? multiplier circuit includes a loop operation circuit that repeatedly perform a predetermined operation by loops, and a setting circuit that sets a required number of loops in the loop operation circuit. The loop operation circuit includes a register that receives an input of an input value, a bit shift circuit that performs bit shift by 2 bits to the right on a value output from the register, and an adder circuit that adds an input value and a value output from the bit shift circuit, and inputs the added value to the register.

Abstract: In an earliest vertical synchronization period after sending an encoded image data is restarted, a first reference image determination circuit determines to employ a local decoded image generated in a vertical synchronization period immediately preceding a vertical synchronization period in which an error occurs among multiple local decoded images stored in a first DRAM as a reference image. In an earliest vertical synchronization period after a decoding circuit is reset, a second reference image determination circuit determines to employ a decoded image generated in the vertical synchronization period immediately preceding the vertical synchronization period in which the error occurs among multiple decoded images stored in a second DRAM as a reference image.

Abstract: If the number of frames in a GOP of an input stream is not less than 15, the GOP is determined as a control unit time. If the number of frames in the GOP is less than 15, the following GOP is connected thereto until the number of frames becomes not less than 15 and the connected GOPs are determined as a control unit time. After correcting the control unit time, the average input bit rate Sn in each control unit time is obtained, and by using information on the input stream including the average input bit rate Sn, a quantization step value of an output stream is calculated.

Abstract: If the number of frames in a GOP of an input stream is not less than 15, the GOP is determined as a control unit time. If the number of frames in the GOP is less than 15, the following GOP is connected thereto until the number of frames becomes not less than 15 and the connected GOPs are determined as a control unit time. After correcting the control unit time, the average input bit rate Sn in each control unit time is obtained, and by using information on the input stream including the average input bit rate Sn, a quantization step value of an output stream is calculated.

Abstract: The image processor includes a ? multiplier circuit that approximately multiplies an input value X by ?. The ? multiplier circuit includes a loop operation circuit that repeatedly perform a predetermined operation by loops, and a setting circuit that sets a required number of loops in the loop operation circuit. The loop operation circuit includes a register that receives an input of an input value, a bit shift circuit that performs bit shift by 2 bits to the right on a value output from the register, and an adder circuit that adds an input value and a value output from the bit shift circuit, and inputs the added value to the register.

Abstract: A quantization step determination part inputs an evaluation value (ACT_MB) indicating the dispersion in a macroblock and its average value (ACT_PIC). A subtracter obtains the difference between these values, and a multiplier multiplies the difference by raq (<1) to obtain a weighting value. Next, an adder adds the weighting value to an average quantization step value of source data, and finally a multiplier multiplies the sum by a step value adjustment factor ? (>1) to obtain a converted quantization step value (Qstep_AVC). This optimizes a bit allocation in accordance with an Activity value of the macroblock, to thereby improve the quality of image.

Abstract: If the number of frames in a GOP of an input stream is not less than 15, the GOP is determined as a control unit time. If the number of frames in the GOP is less than 15, the following GOP is connected thereto until the number of frames becomes not less than 15 and the connected GOPs are determined as a control unit time. After correcting the control unit time, the average input bit rate Sn in each control unit time is obtained, and by using information on the input stream including the average input bit rate Sn, a quantization step value of an output stream is calculated.

Abstract: If the number of frames in a GOP of an input stream is not less than 15, the GOP is determined as a control unit time. If the number of frames in the GOP is less than 15, the following GOP is connected thereto until the number of frames becomes not less than 15 and the connected GOPs are determined as a control unit time. After correcting the control unit time, the average input bit rate Sn in each control unit time is obtained, and by using information on the input stream including the average input bit rate Sn, a quantization step value of an output stream is calculated.

Abstract: A quantization step determination part inputs an evaluation value (ACT_MB) indicating the dispersion in a macroblock and its average value (ACT_PIC). A subtracter obtains the difference between these values, and a multiplier multiplies the difference by raq (<1) to obtain a weighting value. Next, an adder adds the weighting value to an average quantization step value of source data, and finally a multiplier multiplies the sum by a step value adjustment factor ? (>1) to obtain a converted quantization step value (Qstep_AVC). This optimizes a bit allocation in accordance with an Activity value of the macroblock, to thereby improve the quality of image.

Abstract: In an editing apparatus, the work efficiency can be improved comparing to a conventional apparatus. Storage means (14) having a plurality of input ports and at least one output port; and control means (16) for controlling the recording areas of the storage means, in which the different recording area is respectively assigned to each of a plurality of encoding means (11 to 13) as a recording area in which the encoded data is stored, the recording area in which the encoded data has been stored is assigned to the multiplexing unit (15), and the recording area which is different from that of the encoded data is assigned as the recording area in which the multiplexed data is stored are provided, so that the storage means can be commonly used both in the encoding means and the multiplexing means. Thereby, the data transfer between encoding means and the multiplexing means does not performed.

Abstract: In an editing apparatus, the work efficiency can be improved comparing to a conventional apparatus. Storage means (14) having a plurality of input ports and at least one output port; and control means (16) for controlling the recording areas of the storage means, in which the different recording area is respectively assigned to each of a plurality of encoding means (11 to 13) as a recording area in which the encoded data is stored, the recording area in which the encoded data has been stored is assigned to the multiplexing unit (15), and the recording area which is different from that of the encoded data is assigned as the recording area in which the multiplexed data is stored are provided, so that the storage means can be commonly used both in the encoding means and the multiplexing means. Thereby, the data transfer between encoding means and the multiplexing means does not performed.

Abstract: In an editing apparatus, the work efficiency can be improved comparing to a conventional apparatus. Storage means (14) having a plurality of input ports and at least one output port; and control means (16) for controlling the recording areas of the storage means, in which the different recording area is respectively assigned to each of a plurality of encoding means (11 to 13) as a recording area in which the encoded data is stored, the recording area in which the encoded data has been stored is assigned to the multiplexing unit (15), and the recording area which is different from that of the encoded data is assigned as the recording area in which the multiplexed data is stored are provided, so that the storage means can be commonly used both in the encoding means and the multiplexing means. Thereby, the data transfer between encoding means and the multiplexing means does not performed.

Abstract: In an editing apparatus, the work efficiency can be improved comparing to a conventional apparatus. Storage means (14) having a plurality of input ports and at least one output port; and control means (16) for controlling the recording areas of the storage means, in which the different recording area is respectively assigned to each of a plurality of encoding means (11 to 13) as a recording area in which the encoded data is stored, the recording area in which the encoded data has been stored is assigned to the multiplexing unit (15), and the recording area which is different from that of the encoded data is assigned as the recording area in which the multiplexed data is stored are provided, so that the storage means can be commonly used both in the encoding means and the multiplexing means. Thereby, the data transfer between encoding means and the multiplexing means does not performed.

Abstract: In an editing apparatus, the work efficiency can be improved comparing to a conventional apparatus. Storage means (14) having a plurality of input ports and at least one output port; and control means (16) for controlling the recording areas of the storage means, in which the different recording area is respectively assigned to each of a plurality of encoding means (11 to 13) as a recording area in which the encoded data is stored, the recording area in which the encoded data has been stored is assigned to the multiplexing unit (15), and the recording area which is different from that of the encoded data is assigned as the recording area in which the multiplexed data is stored are provided, so that the storage means can be commonly used both in the encoding means and the multiplexing means. Thereby, the data transfer between encoding means and the multiplexing means does not performed.