Patents by Inventor Nobuyuki Takeyasu
Nobuyuki Takeyasu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8372249Abstract: In a method of producing a metal structure by photoreducing metal ion, a substance capable of suppressing growth of metal crystal is added to a medium in which metal ion is dispersed to prevent growth of the metal crystal produced by photoreduction of the metal ion, thereby processing resolution of a metal structure formed of the metal crystal is improved.Type: GrantFiled: March 7, 2012Date of Patent: February 12, 2013Assignee: RikenInventors: Takuo Tanaka, Nobuyuki Takeyasu, Satoshi Kawata
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Publication number: 20120160058Abstract: In a method of producing a metal structure by photoreducing metal ion, a substance capable of suppressing growth of metal crystal is added to a medium in which metal ion is dispersed to prevent growth of the metal crystal produced by photoreduction of the metal ion, thereby processing resolution of a metal structure formed of the metal crystal is improved.Type: ApplicationFiled: March 7, 2012Publication date: June 28, 2012Applicant: RIKENInventors: Takuo TANAKA, Nobuyuki TAKEYASU, Satoshi KAWATA
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Publication number: 20090242381Abstract: In a method of producing a metal structure by photoreducing metal ion, a substance capable of suppressing growth of metal crystal is added to a medium in which metal ion is dispersed to prevent growth of the metal crystal produced by photoreduction of the metal ion, thereby processing resolution of a metal structure formed of the metal crystal is improvedType: ApplicationFiled: March 25, 2009Publication date: October 1, 2009Applicant: RIKENInventors: Takuo Tanaka, Nobuyuki Takeyasu, Satoshi Kuwata
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Patent number: 6063703Abstract: A metal interconnection is prepared by forming an underlying metal film of high melting point metal such as Ti and/or high melting point metal compound such as TiN layers above a semiconductor substrate, plasma etching the surface of the underlying metal film in a gas atmosphere containing chloride, and forming an interconnecting metal film such as Al, Cu, Au and Ag on the underlying metal film. Alternatively, a metal interconnection is prepared by forming an insulating film above a semiconductor substrate, forming connecting holes in the insulating film, forming an underlying metal film such as TiN on the insulating film and the bottom and side wall of the connection holes by a CVD process under controlled conditions, and forming an interconnecting metal film such as Al on the underlying metal film. The TiN film has (111) preferential orientation and the aluminum film has (111) preferential orientation, smooth surface and effective coverage.Type: GrantFiled: May 19, 1998Date of Patent: May 16, 2000Assignee: Kawasaki Steel CorporationInventors: Hiroshi Shinriki, Takeshi Kaizuka, Nobuyuki Takeyasu, Tomohiro Ohta, Eiichi Kondoh, Hiroshi Yamamoto, Tomoharu Katagiri, Tadashi Nakano, Yumiko Kawano
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Patent number: 6001736Abstract: An insulating layer is provided on a semiconductor substrate, a contact hole is formed in the insulating layer, and an underlying metal film is provided on a whole surface of the substrate including inner walls of the contact hole. A surface condition of the underlying metal film is adjusted by a hydrogen plasma treatment. By the hydrogen plasma treatment, a surface of the underlying metal film is hydrogenated and is sputter-etched, so that a disordered film and contaminants adsorbed on the surface of the underlying metal film are removed. Next, aluminum is deposited on the underlying metal film by a chemical vapor deposition process using an organic aluminum compound such as DMAH. The contact hole can be effectively filled with aluminum.Type: GrantFiled: March 4, 1996Date of Patent: December 14, 1999Assignees: Kawasaki Steel Corporation, Tokyo Electron LimitedInventors: Eiichi Kondo, Nobuyuki Takeyasu, Tomohiro Ohta, Yumiko Kawano, Takeshi Kaizuka, Shinpei Jinnouchi
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Patent number: 5973402Abstract: A metal interconnection is prepared by forming an underlying metal film of high melting point metal such as Ti and/or high melting point metal compound such as TiN layers above a semiconductor substrate, plasma etching the surface of the underlying metal film in a gas atmosphere containing chloride, and forming an interconnecting metal film such as Al, Cu, Au and Ag on the underlying metal film. Alternatively, a metal interconnection is prepared by forming an insulating film above a semiconductor substrate, forming connection holes in the insulating film, forming an underlying metal film such as TiN on the insulating film and the bottom and side wall of the connection holes by a CVD process under controlled conditions, and forming an interconnecting metal film such as Al on the underlying metal film. The TiN film has (111) preferential orientation and the aluminum film has (111) preferential orientation, smooth surface and effective coverage.Type: GrantFiled: January 30, 1997Date of Patent: October 26, 1999Assignee: Kawasaki Steel CorporationInventors: Hiroshi Shinriki, Takeshi Kaizuka, Nobuyuki Takeyasu, Tomohiro Ohta, Eiichi Kondoh, Hiroshi Yamamoto, Tomoharu Katagiri, Tadashi Nakano, Yumiko Kawano
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Patent number: 5952723Abstract: A semiconductor device has a multilevel interconnection structure that includes an insulating interlayer formed on a lower wiring layer, a semiconductor substrate, and at least one via hole. The via plug partially fills the via hole, and the upper surface of the via plug may have a convex shape or a surface of the lower wiring layer at a bottom of the via hole may have a concave shape. Where two via holes are present, one via plug substantially fills the shallowest via hole, and partially fills the deepest via hole. The upper wiring layer may be formed over the via plug to fill a remaining portion of the via hole not filled by the via plug.Type: GrantFiled: March 27, 1997Date of Patent: September 14, 1999Assignee: Kawasaki Steel CorporationInventors: Nobuyuki Takeyasu, Hiroshi Yamamoto, Yumiko Kawano, Eiichi Kondoh, Tomoharu Katagiri, Tomohiro Ohta
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Patent number: 5946799Abstract: In a multilevel interconnect structure for use in a semiconductor device including a lower metal wiring having an aluminum or aluminum alloy film and a high melting point metal or high melting metal alloy film, an interlayer insulating film deposited on the lower metal wiring, a via hole formed in the interlayer insulating film, a plug made of aluminum or aluminum alloy and formed in the via hole, and an upper metal wiring having an aluminum or aluminum alloy film and a high melting point metal or high melting point metal alloy film, said plug is directly contacted with the aluminum or aluminum alloy film of at least one of the lower and upper metal wirings to decrease the via resistance without reducing the electromigration reliability.Type: GrantFiled: December 18, 1996Date of Patent: September 7, 1999Assignee: Kawasaki Steel CorporationInventors: Hiroshi Yamamoto, Tomohiro Ohta, Nobuyuki Takeyasu
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Patent number: 5652180Abstract: A semiconductor device with a contact structure includes a silicon substrate, a diffusion region formed in a surface of the silicon substrate, a silicide film of high melting point metal deposited on the diffusion region, an insulating film formed on the silicon substrate, a contact hole formed in the insulating film such that the silicide film is exposed at a bottom of the contact hole, an anti-diffusion film formed on the exposed surface of the silicide film at the bottom of the contact film, a plug formed in the contact hole by a selective Al CVD, and a metal wiring formed on the insulating film such that the metal wiring is electrically connected to the diffusion region by means of the plug, anti-diffusion film and silicide film. The anti-diffusion film may be formed by nitriding the surface of the silicide film.Type: GrantFiled: June 24, 1994Date of Patent: July 29, 1997Assignee: Kawasaki Steel CorporationInventors: Hiroshi Shinriki, Hiroshi Yamamoto, Nobuyuki Takeyasu, Takayuki Komiya, Tomohiro Ohta
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Patent number: 5637534Abstract: A semiconductor device has a multilayered structure that includes an insulating interlayer formed on a lower wiring layer, a semiconductor substrate, and a via hole. The semiconductor device is manufactured by a method that includes plasma etching at least one surface of the insulating interlayer the in an atmosphere having as a major component either a carbonless, chlorine-based gas or a carbonless, chlorine-based gas and an inactive gas in order to remove contaminates that would otherwise promote reactivity with aluminum CVD on the surface of the insulating interlayer.Type: GrantFiled: December 27, 1993Date of Patent: June 10, 1997Assignee: Kawasaki Steel CorporationInventors: Nobuyuki Takeyasu, Hiroshi Yamamoto, Yumiko Kawano, Eiichi Kondoh, Tomoharu Katagiri, Tomohiro Ohta
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Patent number: 5627102Abstract: A metal interconnection is prepared by forming an underlying metal film of high melting point metal such as Ti and/or high melting point metal compound such as TiN layers above a semiconductor substrate, plasma etching the surface of the underlying metal film in a gas atmosphere containing chloride, and forming an interconnecting metal film such as Al, Cu, Au and Ag on the underlying metal film. Alternatively, a metal interconnection is prepared by forming an insulating film above a semiconductor substrate, forming connection holes in the insulating film, forming an underlying metal film such as TiN on the insulating film and the bottom and side wall of the connection holes by a CVD process under controlled conditions, and forming an interconnecting metal film such as Al on the underlying metal film. The TiN film has (111) preferential orientation and the aluminum film has (111) preferential orientation, smooth surface and effective coverage.Type: GrantFiled: December 8, 1995Date of Patent: May 6, 1997Assignee: Kawasaki Steel CorporationInventors: Hiroshi Shinriki, Takeshi Kaizuka, Nobuyuki Takeyasu, Tomohiro Ohta, Eiichi Kondoh, Hiroshi Yamamoto, Tomoharu Katagiri, Tadashi Nakano, Yumiko Kawano
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Patent number: 5627345Abstract: A multilevel interconnect structure for use in a semiconductor device includes a lower metal wiring having an aluminum or aluminum alloy film and a high melting point metal or high melting point metal alloy film. An interlayer insulating film is deposited on the lower metal wiring and a via hole is formed in the interlayer insulating film. A plug made of aluminum or aluminum alloy is formed in the via hole. An upper metal wiring has an aluminum or aluminum alloy film and a high melting point metal or high melting point metal alloy film. The plug directly contacts the aluminum or aluminum alloy film of at least one of the lower and upper metal wirings to decrease the via resistance without reducing the electromigration reliability.Type: GrantFiled: February 18, 1994Date of Patent: May 6, 1997Assignee: Kawasaki Steel CorporationInventors: Hiroshi Yamamoto, Tomohiro Ohta, Nobuyuki Takeyasu
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Patent number: 5486492Abstract: A method of forming a via structure having good characteristics in a semiconductor device having a multilayered wiring structure includes forming a thin film including a high melting point metal or a high melting point metal compound on at least the side wall of a via hole before a via plug including Al or an Al alloy is formed.Type: GrantFiled: October 29, 1993Date of Patent: January 23, 1996Assignee: Kawasaki Steel CorporationInventors: Hiroshi Yamamoto, Nobuyuki Takeyasu, Tomohiro Ohta