Patents by Inventor Nobuyuki Tamura

Nobuyuki Tamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6657893
    Abstract: A memory transistor and a select transistor are disposed side by side on a semiconductor substrate between source/drain diffusion layers thereof, with an intermediate diffusion layer interposed therebetween. The memory transistor includes: a gate insulating film having such a thickness as to allow tunneling current to pass therethrough; a floating gate electrode; an interelectrode insulating film; and a control gate electrode. The select transistor includes a gate insulating film and a select gate electrode. Tunneling current, allowing electrons to pass through the gate insulating film under the floating gate electrode, is utilized during the removal and injection of electrons from/into the floating gate electrode. As a result, higher reliability can be attained and rewriting can be performed at a lower voltage. Also, since the select transistor is provided, reading can also be performed at a lower voltage.
    Type: Grant
    Filed: January 22, 2002
    Date of Patent: December 2, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Keita Takahashi, Masafumi Doi, Hiroyuki Doi, Nobuyuki Tamura, Yasushi Okuda
  • Patent number: 6655666
    Abstract: A liquid-sealed vibration-proof device capable of avoiding leakage of liquid upon press fitting of an outer cylinder is provided. An intermediate ring interposed between the outer cylinder and an antivibratory base is formed at its outer circumferential surface with two projecting streaks, the one on liquid chambers side being formed with cutouts. When the outer cylinder is press fitted to an attachment opening of a vehicle body, the liquid confined in a space enclosed between both projecting streaks can escape to the liquid chambers, so that liquid never leaks outside.
    Type: Grant
    Filed: February 12, 2002
    Date of Patent: December 2, 2003
    Assignee: Toyo Tire & Rubber Co., Ltd.
    Inventors: Nobuyuki Tamura, Shunichi Shinobu
  • Publication number: 20030081606
    Abstract: A digital transmission apparatus, which accommodates a plurality of terminals for exchanging asynchronous frames each including a MAC address, and is used for transmitting the asynchronous frames by putting each of the asynchronous frames in a synchronous frame, includes an address table for storing an address of a group including the digital transmission apparatus, a header-creating unit for creating a header including a communication-destination transmission-apparatus identification including an address of a group including the digital transmission apparatus and a header-adding unit for creating a first frame by adding the header to data of an asynchronous frame received from any one of the terminals.
    Type: Application
    Filed: February 19, 2002
    Publication date: May 1, 2003
    Inventors: Nobuyuki Tamura, Hiroaki Nagao, Sotohiro Kobayashi
  • Publication number: 20030080366
    Abstract: The non-volatile semiconductor memory device has a booster including a capacitor, and a storage circuit including a storage element. The capacitor has a lower electrode, a capacitor capacitance insulating film and an upper electrode. The lower electrode of the capacitor is shaped to have an increased surface area.
    Type: Application
    Filed: October 28, 2002
    Publication date: May 1, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventor: Nobuyuki Tamura
  • Publication number: 20030042089
    Abstract: A liquid-sealed vibration-proof device capable of avoiding leakage of liquid upon press fitting of an outer cylinder is provided. An intermediate ring interposed between the outer cylinder and an antivibratory base is formed at its outer circumferential surface with two projecting streaks, the one on liquid chambers side being formed with cutouts. When the outer cylinder is press fitted to an attachment opening of a vehicle body, the liquid confined in a space enclosed between both projecting streaks can escape to the liquid chambers, so that liquid never leaks outside.
    Type: Application
    Filed: February 12, 2002
    Publication date: March 6, 2003
    Applicant: Toyo Tire & Rubber Co., Ltd.
    Inventors: Nobuyuki Tamura, Shunichi Shinobu
  • Patent number: 6472281
    Abstract: A gate insulator film and a gate electrode are formed on an Si substrate, and a CVD insulator film is deposited thereon to cover the gate electrode. Then, arsenic ions are implanted into the Si substrate from above the CVD insulator film to form LDD layers. After sidewall spacers have been formed over the side faces of the gate electrode with the CVD insulator film interposed therebetween, source/drain layers are formed. Since the LDD layers are formed by implanting dopant ions through the CVD insulator film, the passage of arsenic ions through the ends of the gate electrode can be suppressed. As a result, a semiconductor device suitable for miniaturization can be formed, while suppressing deterioration in insulating properties of the gate oxide film due to the passage of dopant ions through the ends of the gate electrode.
    Type: Grant
    Filed: January 28, 1999
    Date of Patent: October 29, 2002
    Assignee: Matsushita Electronics Corporation
    Inventors: Hiroyuki Doi, Yasushi Okuda, Keita Takahashi, Nobuyuki Tamura
  • Publication number: 20020141340
    Abstract: A transmission apparatus includes a reception line selecting unit, a communication confirming frame transmitting unit, a communication confirming table, and a reception line deciding unit. The reception line selecting unit selects one of several reception lines each formed by the synchronous network. The frame transmitting unit transmits a communication confirming frame to the synchronous network at least at a predetermined period. The communication confirming table stores each reception time of the communication confirming frame received through the synchronous network. The deciding unit decides occurrence of failure on the reception line corresponding to the reception time when a difference between a reception time stored in the table and a present time at the predetermined period exceeds a predetermined value, and transmits instructions for switching the reception line to the reception line selecting unit.
    Type: Application
    Filed: November 7, 2001
    Publication date: October 3, 2002
    Inventors: Nobuyuki Tamura, Hiroaki Nagao, Sotohiro Kobayashi
  • Publication number: 20020064071
    Abstract: A memory transistor and a select transistor are disposed side by side on a semiconductor substrate between source/drain diffusion layers thereof, with an intermediate diffusion layer interposed therebetween. The memory transistor includes: a gate insulating film having such a thickness as to allow tunneling current to pass therethrough; a floating gate electrode; an interelectrode insulating film; and a control gate electrode. The select transistor includes a gate insulating film and a select gate electrode. Tunneling current, allowing electrons to pass through the gate insulating film under the floating gate electrode, is utilized during the removal and injection of electrons from/into the floating gate electrode. As a result, higher reliability can be attained and rewriting can be performed at a lower voltage. Also, since the select transistor is provided, reading can also be performed at a lower voltage.
    Type: Application
    Filed: January 22, 2002
    Publication date: May 30, 2002
    Applicant: Matsushita Electronics Corporation
    Inventors: Keita Takahashi, Masafumi Doi, Hiroyuki Doi, Nobuyuki Tamura, Yasushi Okuda
  • Patent number: 6377490
    Abstract: A memory transistor and a select transistor are disposed side by side on a semiconductor substrate between source/drain diffusion layers thereof, with an intermediate diffusion layer interposed therebetween. The memory transistor includes: a gate insulating film having such a thickness as to allow tunneling current to pass therethrough; a floating gate electrode; an interelectrode insulating film; and a control gate electrode. The select transistor includes a gate insulating film and a select gate electrode. Tunneling current, allowing electrons to pass through the gate insulating film under the floating gate electrode, is utilized during the removal and injection of electrons from/into the floating gate electrode. As a result, higher reliability can be attained and rewriting can be performed at a lower volt age. Also, since the select transistor is provided, reading c an also be performed at a lower voltage.
    Type: Grant
    Filed: October 3, 2000
    Date of Patent: April 23, 2002
    Assignee: Matsushita Electronics Corporation
    Inventors: Keita Takahashi, Masafumi Doi, Hiroyuki Doi, Nobuyuki Tamura, Yasushi Okuda
  • Publication number: 20020041064
    Abstract: A bushing type mount comprising an inner cylinder, an outer cylinder and a rubber-like elastomer interposed between the both cylinders, the outer cylinder being, at axially one extremity side, bent inwardly to form an inner flange, the inner flange being inclined at an intersecting angle made by its flange plane and the axial line of the inner cylinder of 60 to 85 degree, whereby it is possible to reduce a difference between a compressive deformation strain of the elastomer due to the inner flange and a shearing deformation strain occurring around the inner cylinder inboard of the inner flange and to suppress the occurrence of cracking to the utmost, thus enhancing the durability.
    Type: Application
    Filed: September 28, 2001
    Publication date: April 11, 2002
    Inventors: Syunichi Shinobu, Nobuyuki Tamura
  • Publication number: 20010026982
    Abstract: A gate insulator film and a gate electrode are formed on an Si substrate, and a CVD insulator film is deposited thereon to cover the gate electrode. Then, arsenic ions are implanted into the Si substrate from above the CVD insulator film to form LDD layers. After sidewall spacers have been formed over the side faces of the gate electrode with the CVD insulator film interposed therebetween, source/drain layers are formed. Since the LDD layers are formed by implanting dopant ions through the CVD insulator film, the passage of arsenic ions through the ends of the gate electrode can be suppressed. As a result, a semiconductor device suitable for miniaturization can be formed, while suppressing deterioration in insulating properties of the gate oxide film due to the passage of dopant ions through the ends of the gate electrode.
    Type: Application
    Filed: January 28, 1999
    Publication date: October 4, 2001
    Inventors: HIROYUKI DOI, YASUSHI OKUDA, KEITA TAKAHASHI, NOBUYUKI TAMURA
  • Patent number: 6169307
    Abstract: A memory transistor and a select transistor are disposed side by side on a semiconductor substrate between source/drain diffusion layers thereof, with an intermediate diffusion layer interposed therebetween. The memory transistor includes: a gate insulating film having such a thickness as to allow tunneling current to pass therethrough; a floating gate electrode; an interelectrode insulating film; and a control gate electrode. The select transistor includes a gate insulating film and a select gate electrode. Tunneling current, allowing electrons to pass through the gate insulating film under the floating gate electrode, is utilized during the removal and injection of electrons from/into the floating gate electrode. As a result, higher reliability can be attained and rewriting can be performed at a lower voltage. Also, since the select transistor is provided, reading can also be performed at a lower voltage.
    Type: Grant
    Filed: December 8, 1998
    Date of Patent: January 2, 2001
    Assignee: Matsushita Electronics Corporation
    Inventors: Keita Takahashi, Masafumi Doi, Hiroyuki Doi, Nobuyuki Tamura, Yasushi Okuda
  • Patent number: 5737010
    Abstract: A system for connection and disconnection in a multipoint conference system of a cascade configuration, wherein when a list of line numbers of the MCUs and terminals engaging in the conference is input from an input unit of an MCU, a call origination/disconnection table is prepared comprised of the line numbers. When the table is prepared, a call origination/disconnection administrative unit identifies the terminals under the MCU and the other adjoining MCUs, calls and establishes a connection through lines, and, when the connections are completed, circulates a call origination/disconnection table to the other connected MCUs. These MCUs in turn then calls their terminals and their adjoining MCUs and so on until the end MCUs. Further, use is made of a connection list in which connection flags and the order of connection are successively written and use is made of a conference configuration list indicating the actual connections of the MCUs.
    Type: Grant
    Filed: November 2, 1994
    Date of Patent: April 7, 1998
    Assignee: Fujitsu Limited
    Inventors: Takako Yachi, Nobuyuki Tamura, Kazuto Ban, Tohru Andoh
  • Patent number: 5085444
    Abstract: A dust seal for a sliding type bush is interposed between a stationary section and a movable section. The dust seal has a fitting portion fitted to the stationary section, a seal lip portion in sliding contact with the outer circumferential surface of the movable section and a flexible portion interconnecting the fitting portion and the seal lip portion. The dust seal is further provided with an annular projection held in contact with a flange and the outer circumferential surface of the movable section. The seal lip portion is held axially stationarily relative to the movable section.
    Type: Grant
    Filed: June 5, 1990
    Date of Patent: February 4, 1992
    Assignees: Nissan Motor Co., Ltd., Keeper Co., Ltd., Kinugawa Rubber Ind. Co., Ltd.
    Inventors: Takuya Murakami, Toshihiko Kakimoto, Shigeki Dake, Junzo Ishimaru, Yuji Kyoi, Masanao Kameda, Nobuyuki Tamura