Patents by Inventor Nobuyuki Yamanishi

Nobuyuki Yamanishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device having silicon-diffused metal wiring layer and its manufacturing method
    Patent number: 8642467
    Abstract: In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: February 4, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Koichi Ohto, Toshiyuki Takewaki, Tatsuya Usami, Nobuyuki Yamanishi
  • SEMICONDUCTOR DEVICE HAVING SILICON-DIFFUSED METAL WIRING LAYER AND ITS MANUFACTURING METHOD
    Publication number: 20120108060
    Abstract: In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.
    Type: Application
    Filed: January 11, 2012
    Publication date: May 3, 2012
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Koichi OHTO, Toshiyuki TAKEWAKI, Tatsuya USAMI, Nobuyuki YAMANISHI
  • Semiconductor device having silicon-diffused metal wiring layer and its manufacturing method
    Patent number: 8115318
    Abstract: In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: February 14, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Koichi Ohto, Toshiyuki Takewaki, Tatsuya Usami, Nobuyuki Yamanishi
  • Semiconductor device having silicon-diffused metal wiring layer and its manufacturing method
    Patent number: 7842602
    Abstract: In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.
    Type: Grant
    Filed: May 17, 2007
    Date of Patent: November 30, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Koichi Ohto, Toshiyuki Takewaki, Tatsuya Usami, Nobuyuki Yamanishi
  • SEMICONDUCTOR DEVICE HAVING SILICON-DIFFUSED METAL WIRING LAYER AND ITS MANUFACTURING METHOD
    Publication number: 20100224995
    Abstract: In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.
    Type: Application
    Filed: May 4, 2010
    Publication date: September 9, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Koichi Ohto, Toshiyuki Takewaki, Tatsuya Usami, Nobuyuki Yamanishi
  • Semiconductor method having silicon-diffused metal wiring layer
    Patent number: 7737555
    Abstract: In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: June 15, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Koichi Ohto, Toshiyuki Takewaki, Tatsuya Usami, Nobuyuki Yamanishi
  • Single damascene structure semiconductor device having silicon-diffused metal wiring layer
    Patent number: 7687917
    Abstract: In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.
    Type: Grant
    Filed: August 28, 2003
    Date of Patent: March 30, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Koichi Ohto, Toshiyuki Takewaki, Tatsuya Usami, Nobuyuki Yamanishi
  • SEMICONDUCTOR DEVICE HAVING SILICON-DIFFUSED METAL WIRING LAYER AND ITS MANUFACTURING METHOD
    Publication number: 20070212809
    Abstract: In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.
    Type: Application
    Filed: May 17, 2007
    Publication date: September 13, 2007
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Koichi Ohto, Toshiyuki Takewaki, Tatsuya Usami, Nobuyuki Yamanishi
  • Semiconductor device having silicon-diffused metal wiring layer and its manufacturing method
    Publication number: 20070108620
    Abstract: In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.
    Type: Application
    Filed: December 29, 2006
    Publication date: May 17, 2007
    Inventors: Koichi Ohto, Toshiyuki Takewaki, Tatsuya Usami, Nobuyuki Yamanishi
  • Semiconductor device having silicon-including metal wiring layer and its manufacturing method
    Publication number: 20030209738
    Abstract: In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-including metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-including metal layer and the insulating interlayer.
    Type: Application
    Filed: October 28, 2002
    Publication date: November 13, 2003
    Applicant: NEC CORPORATION
    Inventors: Koichi Ohto, Toshiyuki Takewaki, Tatsuya Usami, Nobuyuki Yamanishi
  • Method for manufacturing semiconductor memory devices
    Patent number: 6436761
    Abstract: There is provided a method for manufacturing semiconductor memory devices includes the steps of; forming, for example, an N-type MOS transistor as a memory-cell selecting transistor on a P-type silicon substrate beforehand; forming, as a capacitive-element manufacturing step, an HSG on a first amorphous silicon film which provides a lower electrode; and diffusing an impurity into this HSG and then removing a surface layer of the HSG.
    Type: Grant
    Filed: September 11, 2000
    Date of Patent: August 20, 2002
    Assignee: NEC Corporation
    Inventors: Yoshihiro Harada, Nobuyuki Yamanishi
  • Method for manufacturing semiconductor device
    Patent number: 6399439
    Abstract: Disclosed herein is a method for manufacturing a semiconductor device in which a hemispherical grain size of an inner and an outer wall surfaces of a cylindrical member is uniform to promote the increase of surface areas and to prevent short-circuit between the adjacent cylindrical members. This is achieved (i) by removing an amorphous silicon originally grown layer or (ii) by suppressing the function of the originally grown layer.
    Type: Grant
    Filed: February 18, 1999
    Date of Patent: June 4, 2002
    Assignee: NEC Corporation
    Inventors: Nobuyuki Yamanishi, Toshiyuki Hirota
  • Capacitor formed by lower electrode having inner and outer uneven surfaces
    Patent number: 6307730
    Abstract: A capacitor is constructed by a cylindrical lower capacitor electrode layer having uneven inner and outer surfaces, a capacitor insulating layer formed on the cylindrical lower capacitor electrode layer, and an upper capacitor electrode layer formed on the capacitor insulating layer.
    Type: Grant
    Filed: January 20, 2000
    Date of Patent: October 23, 2001
    Assignee: NEC Corporation
    Inventor: Nobuyuki Yamanishi