Abstract: An output buffer used in, for example, a semiconductor memory device, comprises a first transistor connected between a power potential supply terminal and a data output terminal and a second transistor connected between a reference potential supply terminal and the data output terminal. In response to the data stored in a selected memory cell, either one of the first and second transistors is turned ON to change the potential at the data output terminal to a level corresponding to the data at a first rate. The output buffer further comprises a third transistor connected between the gate of the second transistor and the power potential supply terminal. The third transistor is turned ON before the data stored in the selected memory cell is supplied to the output buffer to vary the potential at the data output terminal to the reference potential at a second rate smaller than the first rate.

Abstract: A memory device provided with initializing function for forcibly setting contents of all the memory cells at the same predetermined logic state is disclosed. The memory device comprises a plurality of word lines, a plurality of digit lines, a plurality of memory cells arranged at the intersections of the word lines and the digit lines, and a word decoder having a plurality of output terminals coupled to the word lines, wherein the word decoder is forcibly set to take at its output terminals a selection level in response to a control signal, and at the same time the digit lines are set at the predetermined logic state in response to the control signal.

Abstract: A semiconductor memory circuit is described for use in a memory array which is capable of permitting data contained in an entire column or in an entire row to be accessed simultaneously. The invented device improves upon the traditional memory circuit, which uses a single word line and two digit lines, by adding a second word line and a third digit line coupled through the gate and drain, respectively, of a transistor device. In a preferred embodiment, all the second word lines of each column are coupled in common to form a common second word line for each column, and all the third digit lines of each row are coupled in common to form a common third digit line for each row. When a signal of a high potential is coupled to the common second word line for a particular column, all the data contained in the memory circuits of that column appears on the common third digit lines.