Patents by Inventor Nobuyuki Yuasa

Nobuyuki Yuasa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8774953
    Abstract: An information processing device according to an embodiment of the present invention includes the following elements: a detection unit configured to detect an amount of change in position of an image data item that is displayed on a display screen; and a processing unit configured to perform image processing on the image data item in accordance with a detection result that is obtained by the detection unit, and to perform audio processing on an audio data item corresponding to the image data item in accordance with the detection result that is obtained by the detection unit.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: July 8, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Nobuyuki Yuasa
  • Patent number: 8112263
    Abstract: To check operation of a circuit to be checked connected to a bus to which at least one master circuit and at least one slave circuit are connected, a model is connected to a bus in place of a master circuit or a slave circuit and cause given signals to be outputted at given timing for checking the operation of the circuit to be checked. Especially, by causing various data transfer to occur at random timing by a plurality of models, it is easy to cause severer than actual conditions to take place easily, enabling to enhance efficiency of checking. For example, when checking operation of a bus arbiter, a plurality of master models are connected in place of a plurality of master circuits to cause a request of bus accessibility to be outputted from each master model at random timing to check arbitration operation of a bus arbiter.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: February 7, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yoshihiro Terashima, Hiroshi Nonoshita, Nobuyuki Yuasa
  • Publication number: 20100302441
    Abstract: An information processing apparatus according to the present invention includes: a transformation unit configured to perform an image data transformation processing to transform a shape of image data; a first determination unit configured to determine an output position of audio data in association with the image data based on transformation information regarding the image data transformation processing performed by the transformation unit; and a configuration unit configured to construct a sound field based on the output position determined by the first determination unit.
    Type: Application
    Filed: May 26, 2010
    Publication date: December 2, 2010
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Nobuyuki Yuasa
  • Publication number: 20090323984
    Abstract: An information processing device according to an embodiment of the present invention includes the following elements: a detection unit configured to detect an amount of change in position of an image data item that is displayed on a display screen; and a processing unit configured to perform image processing on the image data item in accordance with a detection result that is obtained by the detection unit, and to perform audio processing on an audio data item corresponding to the image data item in accordance with the detection result that is obtained by the detection unit.
    Type: Application
    Filed: June 26, 2009
    Publication date: December 31, 2009
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Nobuyuki Yuasa
  • Publication number: 20090210597
    Abstract: To check operation of a circuit to be checked connected to a bus to which at least one master circuit and at least one slave circuit are connected, a model is connected to a bus in place of a master circuit or a slave circuit and cause given signals to be outputted at given timing for checking the operation of the circuit to be checked. Especially, by causing various data transfer to occur at random timing by a plurality of models, it is easy to cause severer than actual conditions to take place easily, enabling to enhance efficiency of checking. For example, when checking operation of a bus arbiter, a plurality of master models are connected in place of a plurality of master circuits to cause a request of bus accessibility to be outputted from each master model at random timing to check arbitration operation of a bus arbiter.
    Type: Application
    Filed: April 29, 2009
    Publication date: August 20, 2009
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Yoshihiro Terashima, Hiroshi Nonoshita, Nobuyuki Yuasa
  • Patent number: 7548841
    Abstract: To check operation of a circuit to be checked connected to a bus to which at least one master circuit and at least one slave circuit are connected, a model is connected to a bus in place of a master circuit or a slave circuit and cause given signals to be outputted at given timing for checking the operation of the circuit to be checked. Especially, by causing various data transfer to occur at random timing by a plurality of models, it is early to cause severer than actual conditions to take place easily, enabling to enhance efficiency of checking. For example, when checking operation of a bus arbiter, a plurality of master models are connected in place of a plurality of master circuits to cause a request of bus accessibility to be outputted from each master model at random timing to check arbitration operation of a bus arbiter.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: June 16, 2009
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yoshihiro Terashima, Hiroshi Nonoshita, Nobuyuki Yuasa
  • Patent number: 7193738
    Abstract: The present invention concerns an image processing device that is connectable to a general-purpose bus of a second image processing apparatus that includes a memory. An image dividing device generates divided images by dividing an original image, and stores the divided images in the memory. An image connecting device generates an original image by connecting divided images stored in the memory.
    Type: Grant
    Filed: July 11, 2002
    Date of Patent: March 20, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventor: Nobuyuki Yuasa
  • Publication number: 20030097248
    Abstract: To check operation of a circuit to be checked connected to a bus to which at least one master circuit and at least one slave circuit are connected, a model is connected to a bus in place of a master circuit or a slave circuit and cause given signals to be outputted at given timing for checking the operation of the circuit to be checked. Especially, by causing various data transfer to occur at random timing by a plurality of models, it is early to cause severer than actual conditions to take place easily, enabling to enhance efficiency of checking. For example, when checking operation of a bus arbiter, a plurality of master models are connected in place of a plurality of master circuits to cause a request of bus accessibility to be outputted from each master model at random timing to check arbitration operation of a bus arbiter.
    Type: Application
    Filed: November 12, 2002
    Publication date: May 22, 2003
    Inventors: Yoshihiro Terashima, Hiroshi Nonoshita, Nobuyuki Yuasa
  • Publication number: 20030016390
    Abstract: The present invention concerns an image processing device that is connectable to a general-purpose bus of a second image processing apparatus that includes a memory. An image dividing device generates divided images by dividing an original image, and stores the divided images in the memory. An image connecting device generates an original image by connecting divided images stored in the memory.
    Type: Application
    Filed: July 11, 2002
    Publication date: January 23, 2003
    Inventor: Nobuyuki Yuasa