Abstract: In one aspect, a method of fabricating a transistor includes depositing a first epitaxial layer; depositing a second epitaxial layer on the first epitaxial layer; forming a single termination trench in the second epitaxial layer; and filling the termination trench with a dielectric. A depth of the termination trench is greater than 10 microns. In another aspect, a transistor includes a first epitaxial layer; a second epitaxial layer on the first epitaxial layer; and a single termination trench in the second epitaxial layer. The termination trench is greater than 10 microns and is filled with a dielectric.

Abstract: In one aspect, a method of fabricating a transistor includes implanting ions into a first portion of a second epitaxial layer to form a recombination region, depositing a second portion of the second epitaxial layer having an n-type dopant on the recombination region, and forming trenches in the second portion of the second epitaxial layer.

Abstract: In one aspect, a method of fabricating a transistor includes depositing a first epitaxial layer, depositing a second epitaxial layer on the first epitaxial layer, implanting the second epitaxial layer to form a p-field termination region, depositing a third epitaxial layer on the p-field termination layer and forming trenches in the third epitaxial layer. The trenches include a trench gate of the transistor and a termination trench.

Abstract: In one aspect, a method of fabricating a transistor includes depositing a first epitaxial layer having a first n-type dopant, depositing a first portion of a second epitaxial layer having a second n-type dopant on the first epitaxial layer, implanting ions into the first portion of the second epitaxial layer to form a recombination region, depositing a second portion of the second epitaxial layer having the second n-type dopant on the recombination region, and forming trenches in the second portion of the second epitaxial layer, wherein the trenches comprise a trench gate of the transistor and a termination trench. The second portion of the second epitaxial layer is thicker than the first portion of the second epitaxial layer.

Abstract: In one aspect, a method of fabricating a transistor includes depositing a first epitaxial layer, depositing a second epitaxial layer on the first epitaxial layer, implanting the second epitaxial layer to form a p-field termination region, depositing a third epitaxial layer on the p-field termination layer and forming trenches in the third epitaxial layer. The trenches include a trench gate of the transistor and a termination trench.

Abstract: In one aspect, a vertical Hall effect sensor includes a semiconductor wafer having a first conductivity type and a plurality of semiconductive electrodes disposed on the semiconductor wafer. The plurality of semiconductive electrodes have the first conductivity type and include a source electrode, a first sensing electrode and a second sensing electrode, arranged such that the source electrode is between the first sensing electrode and the sensing electrode and a first drain electrode and a second drain electrode, arranged such that the first sensing electrode, second sensing electrode, and source electrode are between the first drain electrode and the second drain electrode. The vertical Hall effect sensor also includes a plurality of semiconductor fingers disposed on the semiconductor wafer and interdigitated with the plurality of semiconductive electrodes, the semiconductor fingers having a second conductivity type.

Abstract: In one aspect, a vertical Hall effect sensor includes a semiconductor wafer having a first conductivity type and a plurality of semiconductive electrodes disposed on the semiconductor wafer. The plurality of semiconductive electrodes have the first conductivity type and include a source electrode, a first sensing electrode and a second sensing electrode, arranged such that the source electrode is between the first sensing electrode and the sensing electrode and a first drain electrode and a second drain electrode, arranged such that the first sensing electrode, second sensing electrode, and source electrode are between the first drain electrode and the second drain electrode. The vertical Hall effect sensor also includes a plurality of semiconductor fingers disposed on the semiconductor wafer and interdigitated with the plurality of semiconductive electrodes, the semiconductor fingers having a second conductivity type.

Abstract: In one aspect, a vertical Hall effect sensor includes a semiconductor wafer having a first conductivity type and a plurality of semiconductive electrodes disposed on the semiconductor wafer. The plurality of semiconductive electrodes have the first conductivity type and include a source electrode, a first sensing electrode and a second sensing electrode, arranged such that the source electrode is between the first sensing electrode and the sensing electrode and a first drain electrode and a second drain electrode, arranged such that the first sensing electrode, second sensing electrode, and source electrode are between the first drain electrode and the second drain electrode. The vertical Hall effect sensor also includes a plurality of semiconductor fingers disposed on the semiconductor wafer and interdigitated with the plurality of semiconductive electrodes, the semiconductor fingers having a second conductivity type.

Abstract: In one aspect, a vertical Hall effect sensor includes a semiconductor wafer having a first conductivity type and a plurality of semiconductive electrodes disposed on the semiconductor wafer. The plurality of semiconductive electrodes have the first conductivity type and include a source electrode, a first sensing electrode and a second sensing electrode, arranged such that the source electrode is between the first sensing electrode and the sensing electrode and a first drain electrode and a second drain electrode, arranged such that the first sensing electrode, second sensing electrode, and source electrode are between the first drain electrode and the second drain electrode. The vertical Hall effect sensor also includes a plurality of semiconductor fingers disposed on the semiconductor wafer and interdigitated with the plurality of semiconductive electrodes, the semiconductor fingers having a second conductivity type.

Abstract: A Hall effect transducer in a semiconductor wafer comprises a first layer of semiconducting material, a second layer of semiconducting material, and a contact structure configured to provide a path for electrical current to pass through the second layer. The second layer has higher electron hole mobility than the first layer, and is epitaxially grown atop the first layer.

Abstract: A polysilicon-filled isolation trench in a substrate is effective to isolate adjacent semiconductor devices from one another. A silicon nitride cap is provided to protect the polysilicon in the isolation trench from subsequent field oxidation. The cap has lateral boundaries that extend between the side boundaries of the polysilicon and the sidewalls of the trench. Subsequent field oxide regions formed adjacent to the trench establish a gap dimension from the substrate to a top surface of the field oxide regions adjacent to the polysilicon side boundaries that is no less than half of the field oxide thickness.

Abstract: A Hall effect transducer in a semiconductor wafer comprises a first layer of semiconducting material, a second layer of semiconducting material, and a contact structure configured to provide a path for electrical current to pass through the second layer. The second layer has higher electron hole mobility than the first layer, and is epitaxially grown atop the first layer.

Abstract: A polysilicon-filled isolation trench in a substrate is effective to isolate adjacent semiconductor devices from one another. A silicon nitride cap is provided to protect the polysilicon in the isolation trench from subsequent field oxidation. The cap has lateral boundaries that extend between the side boundaries of the polysilicon and the sidewalls of the trench. Subsequent field oxide regions formed adjacent to the trench establish a gap dimension from the substrate to a top surface of the field oxide regions adjacent to the polysilicon side boundaries that is no less than half of the field oxide thickness.

Abstract: A spacer for a lightly-doped drain MOSFET includes a first spacer layer adjacent to and in contact with a gate region and a lightly-doped region, a second spacer layer adjacent to and in contact with the first layer and a third spacer layer adjacent to and in contact with the second layer.

Abstract: An emitter window for a bipolar junction transistor includes a first emitter window layer adjacent to and in contact with a base region, a second emitter window layer adjacent to and in contact with the first layer and a third emitter window layer adjacent to and in contact with the second layer.