Abstract: The present invention relates to an electrical switchgear unit designed to be fixed onto a fixing support and comprising at least one electrical switching module and at least one module housing a complementary electrical function, at least one of the complementary modules being situated next to at least one of the above-mentioned switching modules, the or each switching module comprising an arc extinguishing chamber. This unit is characterized in that the arc extinguishing chamber of the module situated facing the complementary module presents a cambered face towards the inside of said arc extinguishing chamber so as to create a space E,F inside said chamber enabling a part of the volume of the complementary module to be housed, and in that the ends of said arc extinguishing chamber encroach on the volume of the complementary module.

Abstract: The present invention relates to an electrical switchgear unit designed to be fixed onto a fixing support and comprising at least one electrical switching module and at least one module housing a complementary electrical function, at least one of the complementary modules being situated next to at least one of the above-mentioned switching modules, the or each switching module comprising an arc extinguishing chamber. This unit is characterized in that the arc extinguishing chamber of the module situated facing the complementary module presents a cambered face towards the inside of said arc extinguishing chamber so as to create a space E,F inside said chamber enabling a part of the volume of the complementary module to be housed, and in that the ends of said arc extinguishing chamber encroach on the volume of the complementary module.

Abstract: A system for transmitting HDLC frames on a PCM type link uses a single HDLC circuit and a transposition buffer memory to provide a compact system by economizing on the number of components, enabling operation at high speed without risk of starvation on the PCM link. The system uses a single transposition buffer memory with a read cycle distinct from the write cycle cooperating with a single single-channel HDLC frame formatting circuit. The memory is written with the formatted HDLC frames and read under the control of means for selective sampling in the memory of data for building successive blocks of interleaved channels of the PCM frame.