Abstract: Devices and methods are presented to fabricate diffusion barrier layers on a substrate. Presently, barrier layers comprising a nitride layer and a pure metal layer are formed using a physical vapor deposition (PVD) process that requires multiple ignition steps, and results in nitride-layer thicknesses of no less than 2 nm. This invention discloses devices and process to produce nitride-layers of less than <1 nm, while allowing for formation of a pure metal layer on the nitride-layer without re-igniting the plasma. To achieve this, the flow of nitrogen gas is cut off either before the plasma is ignited, or before the formation of a continuous-flow plasma. This ensures that a limited number of nitrogen atoms is deposited in conjunction with metal atoms on the substrate, thereby allowing for controlled thickness of the nitride layer.

Abstract: Devices and methods are presented to fabricate diffusion barrier layers on a substrate. Presently, barrier layers comprising a nitride layer and a pure metal layer are formed using a physical vapor deposition (PVD) process that requires multiple ignition steps, and results in nitride-layer thicknesses of no less than 2 nm. This invention discloses devices and process to produce nitride-layers of less than <1 nm, while allowing for formation of a pure metal layer on the nitride-layer without re-igniting the plasma. To achieve this, the flow of nitrogen gas is cut off either before the plasma is ignited, or before the formation of a continuous-flow plasma. This ensures that a limited number of nitrogen atoms is deposited in conjunction with metal atoms on the substrate, thereby allowing for controlled thickness of the nitride layer.

Abstract: State of the art Integrated Circuits (ICs) encompass a variety of circuits, which have a wide variety of contact densities as measured in regions from 10 to 1000 microns in size. Fabrication processes for contacts have difficulty with high and low contact densities on the same IC, leading to a high incidence of electrical shorts and reduced operating speed of the circuits. This problem is expected to worsen as feature sizes shrink in future technology nodes. This invention is an electrically non-functional contact, known as a dummy contact, that is utilized to attain a more uniform distribution of contacts across an IC, which allows contact fabrication processes to produce ICs with fewer defects, and a method for forming said dummy contacts in ICs.

Abstract: The present invention provides a method for forming an interconnect on a semiconductor substrate 100. The method includes forming an opening 230 over an inner surface of the opening 130, the depositing forming a reentrant profile near a top portion of the opening 130. A portion of barrier 230 is etched, which removes at least a portion of the barrier 230 to reduce the reentrant profile. The etching also removes at least a portion of the barrier 230 layer at the bottom of the opening 130.

Abstract: A method of fabricating a semiconductor device is provided. An interlayer dielectric layer is formed on one or more semiconductor layers (402). One or more feature regions are formed in the interlayer dielectric layer (404). A first conductive layer is formed in at least a portion of the feature regions and on the interlayer dielectric layer (406)). A first anneal is performed that promotes grain growth of the first conductive layer (408). An additional conductive layer is formed on the first conductive layer (410) and an additional anneal is performed (412) that promotes grain growth of the additional conductive layer and further promotes grain size growth of the first conductive layer. Additional conductive layers can be formed and annealed until a sufficient overburden amount has been obtained. Subsequently, a planarization process is performed that removes excess conductive material and thereby forms and isolates conductive features in the semiconductor device (414).

Abstract: A method for fabricating a seed layer. A seed layer (126) is deposited over a barrier layer (124) using a three-step process comprising a low AC bias power step, a high AC bias power step, and a lower/zero AC bias power step. The low AC bias power step provides low overhang. The high AC bias power step provides good sidewall coverage. The lower/zero AC bias step recovers areas exposed by re-sputtering during the high AC bias power step.

Abstract: A trench (70) is formed in a dielectric layer (20). A first metal layer (80) is formed in the trench using physical vapor deposition. A second metal layer (100) is formed in the trench (70) over the first metal layer (80) using chemical vapor deposition. Copper (110) is used to fill the trench (70) by electroplating copper directly onto the second metal (100).

Abstract: A coil (50) is placed adjacent to a semiconductor wafer (10). An AC excitation current is used to create a changing electromagnetic field (60) is the wafer (10). The wafer is heated by a heat source (20) and the conductivity of the wafer (10) will change as a function of the wafer temperature. Induced eddy currents will cause the inductance of the coil (50) to change and the temperature of the wafer (10) can be determined by monitoring the inductance of the coil (50).

Abstract: According to one embodiment of the invention, a method for forming multiple layers of a semiconductor device is provided. The method includes defining a via through a dielectric layer that overlies a first layer. The first layer comprises a conductive portion that at least partly underlies the via. The method also includes overfilling the via with a dielectric material to form a second layer that overlies the dielectric layer. The method also includes forming a trench that is connected to the via by etching through the second layer and the dielectric material in the via.

Abstract: A method (100) of fabricating an electronic device (200) formed on a semiconductor wafer. The method forms a dielectric layer (226) in a fixed position relative to the wafer, where the dielectric layer comprises an atomic concentration of each of silicon, carbon, and oxygen. After the forming step, the method exposes (118) the electronic device to a plasma such that the atomic concentration of carbon in a portion of the dielectric layer is increased and the atomic concentration of oxygen in a portion of the dielectric layer is decreased. After the exposing step, the method forms a barrier layer (120) adjacent at least a portion of the dielectric layer.

Abstract: A system for constructing semiconductor devices is disclosed. The system comprises a wafer (102) having semiconductor devices (104), a bevel (108), an edge (110), a frontside (111), and a backside (112). The system also has a chamber (107), and a heater (106) coupled to the interior of the chamber (107) and operable to hold and heat the wafer (102). A showerhead (114) is also coupled to the interior of the chamber (107) and is operable to introduce a precursor gas (116) containing copper over the wafer (102). A shield (118) is coupled to the interior of the chamber (107) and is operable to partially shield the bevel (108), the edge (110), and the backside (112) of the wafer (102) from the precursor gas (116). There is an opening (122) in the chamber (107) through which a reactive backside gas (124) may be introduced under the wafer (102). A method for constructing semiconductor devices is disclosed. Step one calls for placing a wafer (102) on a heater (106) in a chamber (107).