Abstract: A processor includes one or more processing units, an execution pipeline and control circuitry. The execution pipeline includes at least first and second pipeline stages that are cascaded so that program instructions, specifying operations to be performed by the processing units in successive cycles of the pipeline, are fetched from a memory by the first pipeline stage and conveyed to the second pipeline stage, which causes the processing units to perform the specified operations. The control circuitry is coupled, upon determining that a program instruction that is present in the second pipeline stage in a first cycle of the pipeline is to be executed again in a subsequent cycle of the pipeline, to cause the execution pipeline to reuse the program instruction in one of the pipeline stages without re-fetching the program instruction from the memory.

Abstract: A novel apparatus for and method of estimating the cable length of an active network link. The cable diagnostics mechanism of the invention is particularly suited for use in estimating the length of Ethernet network between two edges when the link is active, i.e. data is being transmitted in both directions simultaneously and the transmission of test pulses is not possible. The cable length estimation mechanism of the present invention is based on a well-known property of the spectrum of the insertion loss of the cable, namely, the linear relationship between the attenuation of the cable at a given frequency in decibels and the cable length. Information characterizing this relationship is extracted and used to determine the length of the cable.

Abstract: A processor includes one or more processing units, an execution pipeline and control circuitry. The execution pipeline includes at least first and second pipeline stages that are cascaded so that program instructions, specifying operations to be performed by the processing units in successive cycles of the pipeline, are fetched from a memory by the first pipeline stage and conveyed to the second pipeline stage, which causes the processing units to perform the specified operations. The control circuitry is coupled, upon determining that a program instruction that is present in the second pipeline stage in a first cycle of the pipeline is to be executed again in a subsequent cycle of the pipeline, to cause the execution pipeline to reuse the program instruction in one of the pipeline stages without re-fetching the program instruction from the memory.

Abstract: A novel mechanism for sharing filter taps across a plurality of interference cancellers. Each interference canceller may be directed to impairment, such as Ethernet impairments, including Ethernet 1000Base-T impairments. Various interference impairments include echo cancellation, NEXT cancellation and/or other interference detection or cancellation, etc. The hardware requirements of the interference impairment cancellers are reduced by sharing filter taps among the cancellers. In a first embodiment, the taps from a unified filter tap bank are shared across all the interference impairment cancellers for all four channels and over all ports. In a second embodiment, a portion of the taps of each filter are shared wherein each canceller comprises a fixed filter tap portion and a shared filter tap portion. A tap allocation algorithm assigns taps to those cancellers that need them the most. A canceller configuration is selected that yields maximal interference mitigation and the taps are allocated accordingly.

Abstract: A novel mechanism for detecting the presence of powered devices over a network. A unique, infinite pseudo-random sequence of pulses are generated and transmitted over the network to the link partner attached to the other end of the cable. At each time unit, the PSE decides whether or not to transmit a pulse at that time. Thus, the pulses generated have pseudo-random inter-pulse delays between them. In addition, each pulse is pseudo-randomly selected to have either positive or negative polarity. If the link partner is a powered device it will be in loopback mode and the transmitted pulses will be looped back to the transmitter (i.e. the PSE). The PSE, at each time unit regardless of whether or not a pulse was transmitted, opens a search window in which it listens to the RX line for the appropriate expected behavior. If a pulse was transmitted, the PSE expects to see a pulse looped back. Similarly, if no pulse was transmitted, the PSE does not expect to receive a signal during the search window.

Abstract: A novel and useful mechanism for shutting down very small canceller taps that have little influence on the output of the canceller. Disabling or completely disabling these taps results in a significant reduction in power consumption of the circuit incorporating the canceller. Shutting down very low valued canceller taps also results in reduced least mean square (LMS) noise caused by the jittering of the smaller taps of the canceller. Several methods are provided that determine the number and location of the taps to be shutdown. The mechanism of the invention is operative to shut down canceller taps that are lower than a predetermined threshold. Methods include comparing each individual tap to a threshold, comparing an average of each tap to a threshold, comparing groups of taps to a threshold and comparing an average of groups of taps to a threshold. Taps or groups of taps are smaller than the threshold are shutdown thus reducing the power consumption of the canceller.

Abstract: A novel mechanism for sharing filter taps across a plurality of interference cancellers. Each interference canceller may be directed to impairment, such as Ethernet impairments, including Ethernet 1000Base-T impairments. Various interference impairments include echo cancellation, NEXT cancellation and/or other interference detection or cancellation, etc. The hardware requirements of the interference impairment cancellers are reduced by sharing filter taps among the cancellers. In a first embodiment, the taps from a unified filter tap bank are shared across all the interference impairment cancellers for all four channels and over all ports. In a second embodiment, a portion of the taps of each filter are shared wherein each canceller comprises a fixed filter tap portion and a shared filter tap portion. A tap allocation algorithm assigns taps to those cancellers that need them the most. A canceller configuration is selected that yields maximal interference mitigation and the taps are allocated accordingly.

Abstract: A novel apparatus for and method of estimating the cable length of an active network link. The cable diagnostics mechanism of the invention is particularly suited for use in estimating the length of Ethernet network between two edges when the link is active, i.e. data is being transmitted in both directions simultaneously and the transmission of test pulses is not possible. The cable length estimation mechanism of the present invention is based on a well-known property of the spectrum of the insertion loss of the cable, namely, the linear relationship between the attenuation of the cable at a given frequency in decibels and the cable length. Information characterizing this relationship is extracted and used to determine the length of the cable.

Abstract: A novel mechanism for performing high accuracy cable diagnostics. The mechanism utilizes time domain reflectometry (TDR) to detect and identify cable faults, perform estimations of cable length, identify cable topology, identify load and irregular impedance on metallic paired cable, such as twisted pair and coaxial cables. The TDR mechanism transmits pulses whose shapes are programmable and analyzes the signal reflections. The shapes of the pulses transmitted can be optimized in accordance with the channel characteristics. Further, the TDR mechanism is adapted to operative in the presence of high pass filters in the channel.

Abstract: A novel mechanism for detecting the presence of powered devices over a network. A unique, infinite pseudo-random sequence of pulses are generated and transmitted over the network to the link partner attached to the other end of the cable. At each time unit, the PSE decides whether or not to transmit a pulse at that time. Thus, the pulses generated have pseudo-random inter-pulse delays between them. In addition, each pulse is pseudo-randomly selected to have either positive or negative polarity. If the link partner is a powered device it will be in loopback mode and the transmitted pulses will be looped back to the transmitter (i.e. the PSE). The PSE, at each time unit regardless of whether or not a pulse was transmitted, opens a search window in which it listens to the RX line for the appropriate expected behavior. If a pulse was transmitted, the PSE expects to see a pulse looped back. Similarly, if no pulse was transmitted, the PSE does not expect to receive a signal during the search window.

Abstract: A novel mechanism for performing high accuracy cable diagnostics. The mechanism utilizes time domain reflectometry (TDR) to detect and identify cable faults, perform estimations of cable length, identify cable topology, identify load and irregular impedance on metallic paired cable, such as twisted pair and coaxial cables. The TDR mechanism transmits pulses whose shapes are programmable and analyzes the signal reflections. The shapes of the pulses transmitted can be optimized in accordance with the channel characteristics. Further, the TDR mechanism is adapted to operative in the presence of high pass filters in the channel.