Abstract: A semiconductor integrated circuit equipped with an ESD/EOS protection circuit for a plurality of power sources, in which the I/O region is partitioned to form a plurality of partitioned I/O regions each having an ESD/EOS protection circuit for a power source system. Logic circuitry is formed in a core area, which also contains a region where power source system protective elements for the ESD/EOS protection circuit are formed for at least some of partitioned I/O regions. The power source system protective elements formed within the core region may be diodes, condensers, or MOS transistors or other MOS structures. The power source system protective elements may be formed in the same well in the substrate where elements of the logic circuitry is formed, or in separate wells.