Abstract: Power governance circuitry is provided to control a performance level of a processing unit of a processing platform. The power governance circuitry comprises measurement circuitry to measure a current utilization of the processing unit at a current operating frequency and to determine any change in utilization or power and frequency control circuitry is provided to update the current operating frequency to a new operating frequency by determining a new target quantified power expenditure to be applied in a subsequent processing cycle depending on the determination of any change in utilization or power. A new operating frequency is selected to satisfy the new target quantified power based on a scalability function specifying a variation of a given value of utilization or power with the operating frequency. A processing platform and machine readable instructions are provided to set a new quantified target power of a processing unit.

Abstract: Described are mechanisms and methods for applying Machine Learning (ML) techniques for power management at different levels of a power management stack. An apparatus may comprise a first circuitry, a second circuitry, and a third circuitry. The first circuitry may have a plurality of memory registers. The second circuitry may be operable to establish values for a plurality of features based on samples of values of the plurality of memory registers taken at one or more times within a range of time of predetermined length. The third circuitry may be operable to compare the plurality of features against a plurality of learned parameters for a reference workload.

Abstract: Power governance circuitry is provided to control a performance level of a processing unit of a processing platform. The power governance circuitry comprises measurement circuitry to measure a current utilization of the processing unit at a current operating frequency and to determine any change in utilization or power and frequency control circuitry is provided to update the current operating frequency to a new operating frequency by determining a new target quantified power expenditure to be applied in a subsequent processing cycle depending on the determination of any change in utilization or power. A new operating frequency is selected to satisfy the new target quantified power based on a scalability function specifying a variation of a given value of utilization or power with the operating frequency. A processing platform and machine readable instructions are provided to set a new quantified target power of a processing unit.

Abstract: A processor core energy-efficiency core ranking scheme akin to a favored core in a multi-core processor system. The favored core is the energy-efficient core that allows an SoC to use the core with the lowest Vmin for energy-efficiency. Such Vmin values may be fused in appropriate registers or stored in NVM during HVM. An OS scheduler achieves optimal energy performance using the core ranking information to schedule certain applications on the core with lowest Vmin. A bootstrap flow identifies a bootstrap processor core (BSP) as the most energy efficiency core of the SoC and assigns that core the lowest APIC ID value according to the lowest Vmin. Upon reading the fuses or NVM, the microcode/BIOS calculates and ranks the cores. As such, microcode/BIOS calculates and ranks core APIC IDs based on efficiency around LFM frequencies. Based on the calculated and ranked cores, the microcode or BIOS transfers BSP ownership to the most efficiency core.

Abstract: Power governance circuitry is provided to control a performance level of a processing unit of a processing platform. The power governance circuitry comprises measurement circuitry to measure a current utilization of the processing unit at a current operating frequency and to determine any change in utilization or power and frequency control circuitry is provided to update the current operating frequency to a new operating frequency by determining a new target quantified power expenditure to be applied in a subsequent processing cycle depending on the determination of any change in utilization or power. A new operating frequency is selected to satisfy the new target quantified power based on a scalability function specifying a variation of a given value of utilization or power with the operating frequency. A processing platform and machine readable instructions are provided to set a new quantified target power of a processing unit.

Abstract: Described are mechanisms and methods for applying Machine Learning (ML) techniques for power management at different levels of a power management stack. An apparatus may comprise a first circuitry, a second circuitry, and a third circuitry. The first circuitry may have a plurality of memory registers. The second circuitry may be operable to establish values for a plurality of features based on samples of values of the plurality of memory registers taken at one or more times within a range of time of predetermined length. The third circuitry may be operable to compare the plurality of features against a plurality of learned parameters for a reference workload.

Abstract: Power governance circuitry is provided to control a performance level of a processing unit of a processing platform. The power governance circuitry comprises measurement circuitry to measure a current utilization of the processing unit at a current operating frequency and to determine any change in utilization or power and frequency control circuitry is provided to update the current operating frequency to a new operating frequency by determining a new target quantified power expenditure to be applied in a subsequent processing cycle depending on the determination of any change in utilization or power. A new operating frequency is selected to satisfy the new target quantified power based on a scalability function specifying a variation of a given value of utilization or power with the operating frequency. A processing platform and machine readable instructions are provided to set a new quantified target power of a processing unit.

Abstract: Power governance circuitry is provided to control a performance level of a processing unit of a processing platform. The power governance circuitry comprises measurement circuitry to measure a current utilization of the processing unit at a current operating frequency and to determine any change in utilization or power and frequency control circuitry is provided to update the current operating frequency to a new operating frequency by determining a new target quantified power expenditure to be applied in a subsequent processing cycle depending on the determination of any change in utilization or power. A new operating frequency is selected to satisfy the new target quantified power based on a scalability function specifying a variation of a given value of utilization or power with the operating frequency. A processing platform and machine readable instructions are provided to set a new quantified target power of a processing unit.

Abstract: Described are mechanisms and methods for applying Machine Learning (ML) techniques for power management at different levels of a power management stack. An apparatus may comprise a first circuitry, a second circuitry, and a third circuitry. The first circuitry may have a plurality of memory registers. The second circuitry may be operable to establish values for a plurality of features based on samples of values of the plurality of memory registers taken at one or more times within a range of time of predetermined length. The third circuitry may be operable to compare the plurality of features against a plurality of learned parameters for a reference workload.

Abstract: Described are mechanisms and methods for applying Machine Learning (ML) techniques for power management at different levels of a power management stack. An apparatus may comprise a first circuitry, a second circuitry, and a third circuitry. The first circuitry may have a plurality of memory registers. The second circuitry may be operable to establish values for a plurality of features based on samples of values of the plurality of memory registers taken at one or more times within a range of time of predetermined length. The third circuitry may be operable to compare the plurality of features against a plurality of learned parameters for a reference workload.