Abstract: An example self-priming microfluidic structure can include a microfluidic channel including a floor and a ceiling. A channel height is defined as a distance between the floor and the ceiling. A channel height step can be in the floor, or ceiling, or both. The channel height downstream of the channel height step can be greater than the channel height upstream of the channel height step. An interior pillar can be positioned in the microfluidic channel extending from the floor to the ceiling. The interior pillar can include a widening portion at an upstream end of the interior pillar and a tapering portion at a downstream end of the interior pillar. The interior pillar can overlap the channel height step so that the interior pillar is partially upstream of the channel height step and partially downstream of the channel height step.

Abstract: The present subject matter relates to disposing memory banks and select register. In an example implementation, a plurality of memory banks is arranged to form a group of memory banks. Each memory bank includes a plurality of memory units. At least one select register generates a select signal to access the memory units in the plurality of memory banks. The at least one select register is disposed at an end of the group of memory banks.

Abstract: The present subject matter relates to accessing memory units in a memory bank. In an example implementation, a bank select transistor is common to a plurality of memory units in a memory bank. The bank select transistor facilitates accessing a memory unit of the plurality of memory units based on a bank select signal.

Abstract: The present subject matter relates to disposing memory banks and select register. In an example implementation, a plurality of memory banks is arranged to form a group of memory banks. Each memory bank includes a plurality of memory units. At least one select register generates a select signal to access the memory units in the plurality of memory banks. The at least one select register is disposed at an end of the group of memory banks.

Abstract: The present subject matter relates to disposing memory banks and select register. In an example implementation, a plurality of memory banks is arranged to form a group of memory banks. Each memory bank includes a plurality of memory units. At least one select register generates a select signal to access the memory units in the plurality of memory banks. The at least one select register is disposed at an end of the group of memory banks.

Abstract: The present subject matter relates to accessing memory units in a memory bank. In an example implementation, a bank select transistor is common to a plurality of memory units in a memory bank. The bank select transistor facilitates accessing a memory unit of the plurality of memory units based on a bank select signal.

Abstract: The present subject matter relates to accessing memory units in a memory bank. In an example implementation, a bank select transistor is common to a plurality of memory units in a memory bank. The bank select transistor facilitates accessing a memory unit of the plurality of memory units based on a bank select signal.

Abstract: The present subject matter relates to disposing memory banks and select register. In an example implementation, a plurality of memory banks is arranged to form a group of memory banks. Each memory bank includes a plurality of memory units. At least one select register generates a select signal to access the memory units in the plurality of memory banks. The at least one select register is disposed at an end of the group of memory banks.

Abstract: The present subject matter relates to accessing memory units in a memory bank. In an example implementation, a bank select transistor is common to a plurality of memory units in a memory bank. The bank select transistor facilitates accessing a memory unit of the plurality of memory units based on a bank select signal.