Patents by Inventor Noorshaheen Mavungal Noorudheen

Noorshaheen Mavungal Noorudheen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11977755
    Abstract: A front-end firmware component of a memory sub-system receives a first request to perform a first set of initialization operations and initiates a first set of initialization operations for the front-end component in parallel with initiating a second set of initialization operations for a back-end component. Responsive to completing the first set of initialization operations, the front-end component sends a first notification to a host computer system to indicate that the front-end component is available to respond to requests for configuration data associated with the memory sub-system, receives a second request from the host computer system for a configuration data associated with the memory sub-system, and responsive to receiving the second request from the host computer system before the back-end component has completed the second set of initialization operations, provides the configuration data to the host computer system.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: May 7, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Ximin Shan, Venkata Naga Lakshman Pasala, Noorshaheen Mavungal Noorudheen
  • Publication number: 20240004745
    Abstract: Aspects of the present disclosure configure a system component, such as memory sub-system controller, to pause memory sub-system operations in response to a critical event. The memory sub-system controller can include a front-end (FE) device that stores critical event trigger data in trigger event logic registers. Upon detecting that operations of the memory sub-system, such as command latencies, correspond to the critical event trigger data, the FE device performs pause operations, including storing a state of the memory sub-system and transmitting an interrupt signal to the memory sub-system controller, such as a CPU, to initiate debugging operations.
    Type: Application
    Filed: September 9, 2022
    Publication date: January 4, 2024
    Inventors: Noorshaheen Mavungal Noorudheen, Sudhakar Ravindra Parab, Sanjay Tanaji Shinde
  • Publication number: 20240004641
    Abstract: Aspects of the present disclosure configure a system component, such as memory sub-system controller, to update firmware using a virtual slot. The memory sub-system controller receives an image that includes a firmware update and performs a verification of the image. The verified firmware update is stored in a storage location on a set of memory components prior to receiving a commit request from a host. After the commit request is received from the host, a firmware slot identified by the commit request is linked to the verified image that is stored in the storage location. The memory sub-system is then booted from the firmware slot using the verified image that is stored in the storage location.
    Type: Application
    Filed: September 9, 2022
    Publication date: January 4, 2024
    Inventors: Noorshaheen Mavungal Noorudheen, Shalu Agrawal
  • Publication number: 20230064014
    Abstract: A front-end firmware component of a memory sub-system receives a first request to perform a first set of initialization operations, where the front-end component communicates with a back-end component in a data path associated with a memory device of the memory sub-system; responsive to receiving the first request, initiates the a first set of initialization operations for the front-end component in parallel with initiating a second set of initialization operations for the back-end component; responsive to completing the first set of initialization operations, sends a first notification to a host computer system to indicate that the front-end component is available to respond to requests for configuration data associated with the memory sub-system; receives a second request from the host computer system for a configuration data associated with the memory sub-system, where the second request is received before the back-end component has completed the second set of initialization operations; and responsive to r
    Type: Application
    Filed: July 29, 2022
    Publication date: March 2, 2023
    Inventors: Ximin Shan, Venkata Naga Lakshman Pasala, Noorshaheen Mavungal Noorudheen
  • Publication number: 20230026712
    Abstract: A description of a snapshot to be generated is received by a local media controller of a memory device, from a memory sub-system controller. The description comprises a memory address range of a memory device. Responsive to detecting a triggering event, a snapshot of the memory address range of the memory device is generated in view of the description. The snapshot is stored to a destination address. The memory sub-system controller is notified of the triggering event.
    Type: Application
    Filed: July 22, 2021
    Publication date: January 26, 2023
    Inventor: Noorshaheen Mavungal Noorudheen
  • Patent number: 9286209
    Abstract: A RAID storage system serializes data blocks to be stored in a RAID storage array and uses a primary map table and a number of secondary map tables to relate host addresses to logical block addresses in the storage array. Secondary map tables and other metadata can be cached from the storage array. The dual or two-tier map scheme and metadata caching promote scalability.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: March 15, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Anant Baderdinni, Noorshaheen Mavungal Noorudheen
  • Publication number: 20150301934
    Abstract: A RAID storage system serializes data blocks to be stored in a RAID storage array and uses a primary map table and a number of secondary map tables to relate host addresses to logical block addresses in the storage array. Secondary map tables and other metadata can be cached from the storage array. The dual or two-tier map scheme and metadata caching promote scalability.
    Type: Application
    Filed: May 9, 2014
    Publication date: October 22, 2015
    Applicant: LSI Corporation
    Inventors: Anant Baderdinni, Noorshaheen Mavungal Noorudheen