Abstract: A method of designing a semiconductor device is provided. The method includes a step of defining a dummy structure area on the floorplan layout of the semiconductor device. The method also includes a step of adding dummy cells to the dummy structure area. Each dummy cell may be associated with a different data type. The method may improve a design optimization process of dummy cells on the semiconductor device layout by automating the removal process of dummy cells to optimize dummy density. Apart from that, semiconductor devices that are manufactured using the described method, and an apparatus to perform the steps described in the method are also described.

Abstract: An IC design that has an ESD transistor is disclosed. The IC includes a transistor, a ballast resistor, a routing structure and a coupling. The transistor includes a gate, a source and a drain. The ballast resistor is extending parallel to the gate of the transistor. The coupling connects the source of the drain of the transistor the ballast resistor. The routing structure connects the ballast resistor to the remaining of the circuitry. A method to design the IC is also disclosed. The ESD transistor provides means of protection against the ESD surges.