Abstract: This circuit is inserted between a terminal (RGB) and a line (LI). The signal of the input terminal (RGB) is applied to the base of a bipolar amplifier transistor (T2) mounted with a top load (LR1) and a bottom load (LR2). A series transistor (T1) mounted in series in the main signal path has its collector wired up as an electrode for receiving the input signal, its emitter feeds a line (LI), and its base is linked by a resistor to the collector of the second transistor.

Abstract: A video signal generator comprises a frequency divider (5), connected to the pixel oscillator (4) to deliver a width-modulated control signal (Ftr) at a lower frequency than, but synchronized with, the pixel signal. A local pixel synchronizing signal generator (14) includes a PLL-loop provided, in succession, with a first division stage (10) and with a second division stage (11) which bring the pixel frequency (fpx) down to the line frequency (ftr). Between the first division stage (10) and the second division stage, the signal is fed into a divider (12) whose output is connected to the clock input (Cp) of a D-type flip-flop, the input D of which is connected to the control signal (Ftr) and the output (Q) of which delivers a signal (Fpwm) for adjusting the screen.