Abstract: A computer-implemented method for automated operation of network devices within a home communication network includes detecting actuator actions for a plurality of actuators within the home communication network, each actuator of the plurality of actuators configured to change a state of at least one network device. The detected actuator actions are correlated with one or more sensor values from a plurality of sensors within the home communication network to generate configuration data. The configuration data includes a trigger graph with one or more trigger conditions and an action graph corresponding to the trigger graph. The action graph indicates one or more actuator actions associated with at least one actuator of the plurality of actuators. Upon detecting a trigger condition of the one or more trigger conditions, the at least one actuator of the plurality of actuators is triggered to perform the one or more actions indicated by the action graph.

Abstract: A method performed by a computing system that includes multiple compute nodes and a memory node separate from the multiple compute nodes. The method comprises executing a task using the multiple compute nodes; recurrently receiving snapshots at the memory node from the multiple compute nodes, each snapshot including an instance of a task database; setting a current checkpoint by storing a task database instance corresponding to the current checkpoint when all received snapshots match; and rolling back the task database to a previous checkpoint when detecting unmatching snapshots received from the multiple compute nodes, including the memory node distributing a correct checkpoint task database instance to at least one compute node of the multiple compute nodes.

Abstract: A computer-implemented method for automated operation of network devices within a home communication network includes detecting actuator actions for a plurality of actuators within the home communication network, each actuator of the plurality of actuators configured to change a state of at least one network device. The detected actuator actions are correlated with one or more sensor values from a plurality of sensors within the home communication network to generate configuration data. The configuration data includes a trigger graph with one or more trigger conditions and an action graph corresponding to the trigger graph. The action graph indicates one or more actuator actions associated with at least one actuator of the plurality of actuators. Upon detecting a trigger condition of the one or more trigger conditions, the at least one actuator of the plurality of actuators is triggered to perform the one or more actions indicated by the action graph.

Abstract: A method of communicating data over a Peripheral Component Interconnect Express (PCIe) Non-Transparent Bridge (NTB) comprising transmitting a first posted write message to a remote processor via the NTB, wherein the first posted write message indicates an intent to transfer data to the remote processor, and receiving a second posted write message in response to the first posted write message, wherein the second posted write message indicates a destination address list for the data. Also disclosed is a method of communicating data over a PCIe NTB comprising transmitting a first posted write message to a remote processor via the NTB, wherein the first posted write message comprises a request to read data, and receiving a data transfer message comprising at least some of the data requested by the first posted write message.

Abstract: A peripheral component interconnect express PCI-e network system having a processor for (a) assigning addresses to the PCI-e topology tree, comprising: traversing, at a given level and in a breadth direction, down-link couplings to an interconnection; ascertaining, at the level, which of the down-link couplings are connected to nodes; assigning, at the level, addresses to nodes of ascertained down-link coupling having nodes; and (b) propagating, a level, comprising: traversing, at the level and in a depth direction, down-link couplings to the interconnection of the PCI-e network, ascertaining, at the level, which of the downlink couplings are coupled to other interconnections in the depth direction, consecutively proceeding in the depth direction, to a next level of the down-link coupling of a next interconnection; and alternatively repeating (a) and (b) until the nodes are assigned addresses within the PCI-e tree topology network.

Abstract: Systems and methods for offloading computations from a CPU directly to an accelerator engine are disclosed. One embodiment includes determining a function of an application to be offloaded from a CPU to an accelerator engine, locating data within a file necessary to perform the functions, programming a logic of the accelerator engine based on the function to be offloaded, programming a DMA engine to move a copy the data from a secondary storage device to the accelerator engine, and processing the data at the accelerator engine using the programmed logic.

Abstract: A method of communicating data over a Peripheral Component Interconnect Express (PCIe) Non-Transparent Bridge (NTB) comprising transmitting a first posted write message to a remote processor via the NTB, wherein the first posted write message indicates an intent to transfer data to the remote processor, and receiving a second posted write message in response to the first posted write message, wherein the second posted write message indicates a destination address list for the data. Also disclosed is a method of communicating data over a PCIe NTB comprising transmitting a first posted write message to a remote processor via the NTB, wherein the first posted write message comprises a request to read data, and receiving a data transfer message comprising at least some of the data requested by the first posted write message.

Abstract: A method of communicating data over a Peripheral Component Interconnect Express (PCIe) Non-Transparent Bridge (NTB) comprising transmitting a first posted write message to a remote processor via the NTB, wherein the first posted write message indicates an intent to transfer data to the remote processor, and receiving a second posted write message in response to the first posted write message, wherein the second posted write message indicates a destination address list for the data. Also disclosed is a method of communicating data over a PCIe NTB comprising transmitting a first posted write message to a remote processor via the NTB, wherein the first posted write message comprises a request to read data, and receiving a data transfer message comprising at least some of the data requested by the first posted write message.

Abstract: An apparatus comprising at least one receiver configured to receive a traffic flow, receive information comprising a set of functions and an order of the set from a controller, and a processor coupled to the at least one receiver and configured to assign the traffic flow to one or more resources, determine a processing schedule for the traffic flow, and process the traffic flow by the set of functions, following the order of the set, using the one or more resources, and according to the processing schedule.

Abstract: A system comprising a unified interconnect network, a plurality of process memory modules, and a plurality of processor modules configured to share access to the memory modules via the unified interconnect network. Data may be communicated between a plurality of processor modules and a plurality of shared resource pools via a unified interconnect network, wherein the communications comprise a protocol that is common to all resource pools, and wherein each resource pool comprises a plurality of resource modules each configured to perform a common function. Further, a network interface controller (NIC) module may be configured to receive data from a plurality of processor modules via a unified interconnect network, and provide core network connectivity to the processor modules.

Abstract: Embodiments of the present invention provide a data processing system and a data processing method. An MMIO address of a data request is obtained, where data stored in a PCIe storage device can be directly obtained from the MMIO address, and according to the MMIO address, a network adapter can directly read the data from the PCIe storage device of the data processing system, and transmit the data to a second data processing system, or directly write the data received from the second data processing system into the PCIe storage device. Therefore, the processing system can implement transmitting data directly from the PCIe storage device to the network adapter without using memory. During data transmission between the two data processing systems, a usage ratio of a resource, such as memory and a CPU, is reduced, and efficiency of data transmission is improved.

Abstract: Embodiments of the present invention provide a solution for managing inter-domain resource allocation in a Peripheral Component Interconnect-Express (PCIe) network. One processor among a plurality of link processors is elected as a management processor. The management processor obtains information about available resources of PCIe network. When a resource request from a request processor is received, the management processor allocates a resource of the available resources to the requesting processor. The management processor instructs one or more link processors to program one or more inter-domain NTBs through which the traffic between the allocated resource and the requesting processor is going to flow according to the memory address information of the allocated resource, to allow cross-domain resource access between the requesting processor and the allocated resource.

Abstract: In a high-dimensional PCI-Express (PCIe) network, implementation of alternative paths is accomplished to facilitate flexible topology implementation and network domain scaling while enabling improved communication latency. Different portions of the PCIe tree structure are connected to allow a shorter path for communications by utilizing a bridge circuit configured as an end-point with respect to two switches that are not directly connected in the PCIe tree topology. The bridge circuit performs address translations to allow communications from one switch to be passed via the bridge circuit to the other switch.

Abstract: An apparatus for initialization. The apparatus includes a management I/O device controller for managing initialization of a plurality of I/O devices coupled to a PCI-Express (PCIe) fabric. The management I/O device controller is configured for receiving a request to register a target interrupt register address of a first worker computing resource, wherein the target interrupt register address is associated with a first interrupt generated by a first I/O device coupled to the PCIe fabric. A mapping module of the management I/O device controller is configured for mapping the target interrupt register address to a mapped interrupt register address of a domain in which the first I/O device resides. A translating interrupt register table includes a plurality of mapped interrupt register addresses in the domain that is associated with a plurality of target interrupt register addresses of a plurality of worker computing resources.

Abstract: An apparatus for initialization. The apparatus includes a management I/O device controller for managing initialization of a plurality of I/O devices coupled to a PCI-Express (PCIe) fabric. The management I/O device controller is configured for receiving a request to register a target interrupt register address of a first worker computing resource, wherein the target interrupt register address is associated with a first interrupt generated by a first I/O device coupled to the PCIe fabric. A mapping module of the management I/O device controller is configured for mapping the target interrupt register address to a mapped interrupt register address of a domain in which the first I/O device resides. A translating interrupt register table includes a plurality of mapped interrupt register addresses in the domain that is associated with a plurality of target interrupt register addresses of a plurality of worker computing resources.

Abstract: Embodiments of the present invention provide a data processing system and a data processing method. An MMIO address of a data request is obtained, where data stored in a PCIe storage device can be directly obtained from the MMIO address, and according to the MMIO address, a network adapter can directly read the data from the PCIe storage device of the data processing system, and transmit the data to a second data processing system, or directly write the data received from the second data processing system into the PCIe storage device. Therefore, the processing system can implement transmitting data directly from the PCIe storage device to the network adapter without using memory. During data transmission between the two data processing systems, a usage ratio of a resource, such as memory and a CPU, is reduced, and efficiency of data transmission is improved.

Abstract: A peripheral component interconnect express PCI-e network system having a processor for (a) assigning addresses to the PCI-e topology tree, comprising: traversing, at a given level and in a breadth direction, down-link couplings to an interconnection; ascertaining, at the level, which of the down-link couplings are connected to nodes; assigning, at the level, addresses to nodes of ascertained down-link coupling having nodes; and (b) propagating, a level, comprising: traversing, at the level and in a depth direction, down-link couplings to the interconnection of the PCI-e network, ascertaining, at the level, which of the downlink couplings are coupled to other interconnections in the depth direction, consecutively proceeding in the depth direction, to a next level of the down-link coupling of a next interconnection; and alternatively repeating (a) and (b) until the nodes are assigned addresses within the PCI-e tree topology network.

Abstract: In a high-dimensional PCI-Express (PCIe) network, implementation of alternative paths is accomplished to facilitate flexible topology implementation and network domain scaling while enabling improved communication latency. Different portions of the PCIe tree structure are connected to allow a shorter path for communications by utilizing a bridge circuit configured as an end-point with respect to two switches that are not directly connected in the PCIe tree topology. The bridge circuit performs address translations to allow communications from one switch to be passed via the bridge circuit to the other switch.

Abstract: An apparatus for initialization. The apparatus includes a management I/O device controller for managing initialization of a plurality of I/O devices coupled to a PCI-Express (PCIe) fabric. The management I/O device controller is configured for receiving a request to register a target interrupt register address of a first worker computing resource, wherein the target interrupt register address is associated with a first interrupt generated by a first I/O device coupled to the PCIe fabric. A mapping module of the management I/O device controller is configured for mapping the target interrupt register address to a mapped interrupt register address of a domain in which the first I/O device resides. A translating interrupt register table includes a plurality of mapped interrupt register addresses in the domain that is associated with a plurality of target interrupt register addresses of a plurality of worker computing resources.

Abstract: Systems and methods for offloading computations from a CPU directly to an accelerator engine are disclosed. One embodiment includes determining a function of an application to be offloaded from a CPU to an accelerator engine, locating data within a file necessary to perform the functions, programming a logic of the accelerator engine based on the function to be offloaded, programming a DMA engine to move a copy the data from a secondary storage device to the accelerator engine, and processing the data at the accelerator engine using the programmed logic.