Patents by Inventor Norbert Galster

Norbert Galster has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130199825
    Abstract: Disclosed are composite build-up materials for the manufacture of printed circuit boards, IC substrates, chip packages and the like. The composite build-up materials are suitable for embedding circuitry such as microvias, trenches and pads. The composite build-up materials comprise a carrier layer (1), a resin layer without reinforcement (2), and a resin layer with reinforcement (3). The circuitry (9) is embedded into the resin layer without reinforcement (2).
    Type: Application
    Filed: October 21, 2011
    Publication date: August 8, 2013
    Applicant: ATOTECH DEUTSCHLAND GMBH
    Inventors: Alex Bruderer, Norbert Galster, Jurgen Kress, Michel Probst
  • Publication number: 20130199832
    Abstract: Disclosed are composite build-up materials for the manufacture of printed circuit boards, IC substrates, chip packages and the like. The composite build-up materials are suitable for embedding active components such as micro chips. The composite build-up materials comprise a carrier layer (1), a resin layer with reinforcement (2), and a resin layer without reinforcement (3). The active component (6) is embedded into the resin layer without reinforcement (6).
    Type: Application
    Filed: October 21, 2011
    Publication date: August 8, 2013
    Applicant: ATOTECH DEUTSCHLAND GMBH
    Inventors: Norbert Galster, Jurgen Kress, Hugh Laver
  • Publication number: 20050277244
    Abstract: A microtool for embossing structures into a substrate is fastened to an object, such as a press plate, by sintering, preferably pressure sintering. An insight underlying the invention is the fact that such a sintering or pressure sintering method provides a sufficiently reliable, strong, heat conducting and/or dimensionally stable connection, even for a hot embossing process, where at elevated temperatures, pressures of 10-300 bar and tensile forces of up to 100-200 bar may act upon the connection, and where a dimensional stability of down to the micrometer scale may be required. According to a preferred embodiment, the forming temperature of a pressure sintered connection equals the embossing temperature, i.e. the working temperature of the tool.
    Type: Application
    Filed: November 21, 2002
    Publication date: December 15, 2005
    Inventors: Norbert Galster, Ignaz Egger, Philippe Steiert, Gerhard Palm
  • Patent number: 6475876
    Abstract: In a process for fabricating a semiconductor component, in particular a semiconductor diode, a semiconductor substrate (1) is provided with metal layers (3, 4) in order to form electrode terminals and with passivation (2), and is exposed to particle irradiation (P) in order to adjust the carrier lifetime. This being the case, at least the metal layer (3) on the irradiation side and the passivation (2) are not applied until after the particle irradiation (P). As a result, a continuous defect region (5), which precludes undesired edge effects, is obtained in the semiconductor substrate (1).
    Type: Grant
    Filed: August 16, 1999
    Date of Patent: November 5, 2002
    Assignee: ABB Schweiz Holding AG
    Inventors: Norbert Galster, Stefan Linder
  • Patent number: 6469368
    Abstract: In a method for producing a high-speed power diode with soft recovery, in which method the carrier life within the associated semiconductor substrate (10) is governed by first, unmasked bombardment (14) with an axial profile and by subsequent, second, masked bombardment (15) with a lateral profile, improved reverse characteristics are achieved in that the first, unmasked bombardment is ion bombardment (14) which governs the switching response of the power diode and in that the second, masked bombardment is electron bombardment (15), which reduces the active area of the power diode. In a power diode equipped with such a semiconductor substrate (10), the thermal resistance Rth is reduced in relation to the active area of the power diode.
    Type: Grant
    Filed: July 3, 2001
    Date of Patent: October 22, 2002
    Assignee: ABB Schweiz AG
    Inventor: Norbert Galster
  • Publication number: 20020045321
    Abstract: In a process for fabricating a semiconductor component, in particular a semiconductor diode, a semiconductor substrate (1) is provided with metal layers (3, 4) in order to form electrode terminals and with passivation (2), and is exposed to particle irradiation (P) in order to adjust the carrier lifetime. This being the case, at least the metal layer (3) on the irradiation side and the passivation (2) are not applied until after the particle irradiation (P). As a result, a continuous defect region (5), which precludes undesired edge effects, is obtained in the semiconductor substrate (1).
    Type: Application
    Filed: August 16, 1999
    Publication date: April 18, 2002
    Inventors: NORBERT GALSTER, STEFAN LINDER
  • Publication number: 20020003287
    Abstract: In a method for producing a high-speed power diode with soft recovery, in which method the carrier life within the associated semiconductor substrate (10) is governed by first, unmasked bombardment (14) with an axial profile and by subsequent, second, masked bombardment (15) with a lateral profile, improved reverse characteristics are achieved in that the first, unmasked bombardment is ion bombardment (14) which governs the switching response of the power diode and in that the second, masked bombardment is electron bombardment (15), which reduces the active area of the power diode.
    Type: Application
    Filed: July 3, 2001
    Publication date: January 10, 2002
    Inventor: Norbert Galster
  • Patent number: 6159830
    Abstract: In a process for adjusting the carrier lifetime in a semiconductor component (1) by means of particle irradiation (P), at least two defect regions (10, 11, 12, 13) are produced in the semiconductor component (1). In this process, a particle beam (P), consisting of particles (a, b, c, d) with at least approximately the same initial energy, is acted on by at least one means (2), before reaching the semiconductor component (1), in such a way that the particles (a, b, c, d) subsequently have different energy values, at least two energy value groups being distinguishable. It is thereby possible, with a single particle irradiation operation, to produce an arbitrary number of defect regions whose arrangement and weighting is arbitrarily selectable.
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: December 12, 2000
    Assignee: Asea Brown Boveri AG
    Inventors: Norbert Galster, Pavel Hazdra, Jan Vobecky
  • Patent number: 5869358
    Abstract: A two-stage method is proposed for producing a highly transparent anode emitter (2) in a GTO (1). In a first step, an anode emitter (2) is indiffused whose thickness is greater than 0.5 .mu.m and whose doping concentration is greater than 10.sup.17 cm.sup.-3. In a second step, the emitter efficiency of the anode emitter (2) is subsequently reduced to a desired degree by local carrier life setting.
    Type: Grant
    Filed: September 4, 1997
    Date of Patent: February 9, 1999
    Assignee: Asea Brown Boveri AG
    Inventors: Norbert Galster, Sven Klaka, Andre Weber