Abstract: A semiconductor memory produced in a unipolar technology includes a cell which has a pair of inversion capacitors with one terminal of each capacitor connected to one of a pair of bit/sense lines, the other terminal of each capacitor is coupled to a source of charges by a pulse from a word line. The charges produced from the source may be in the form of pulses injected into the capacitors. To provide a word organized array of these cells, each word includes a source of charges produced at the surface of a semiconductor substrate and a plurality of pairs of inversion capacitors formed also at the surface of the semiconductor in spaced apart relationship from the charge source. Information is written into the pairs of capacitors by applying complementary voltages to each pair of bit/sense lines coupled to the pairs of capacitors while a word pulse produces inversion layers at the surface of the substrate between the capacitors to interconnect serially the charge source with each of the capacitors.