Patents by Inventor Norbert Hagspiel
Norbert Hagspiel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8995210Abstract: A method of avoiding a write collision in single port memory devices from two or more independent write operations is described. A first write operation having a first even data object and a first odd data object is received from a first data sender. A second write operation having a second even data object and a second odd data object is received from a second data sender at substantially the same time as the first write operation. The second write operation is delayed so that the first even data object writes to a first single port memory device at a different time than the second even data object writes to the first single port memory device. The second write operation is delayed so that the first odd data object writes to a second single port memory device at a different time than the second odd data object.Type: GrantFiled: November 26, 2013Date of Patent: March 31, 2015Assignee: International Business Machines CorporationInventors: Norbert Hagspiel, Sascha Junghans, Matthias Klein, Joerg Walter
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Patent number: 8850129Abstract: A system and computer implemented method for storing of data in the memory of a computer system in order at a fast rate is provided. The method includes launching a first store to memory. A wait counter is initiated. A second store to memory is speculatively launched when the wait counter expires. The second store to memory is cancelled when the second store achieves coherency prior to the first store to memory.Type: GrantFiled: June 24, 2010Date of Patent: September 30, 2014Assignee: International Business Machines CorporationInventors: Norbert Hagspiel, Matthias Klein, Ulrich Mayer, Robert J. Sonnelitter, III, Gary E. Strait, Hanno Ulrich
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Patent number: 8762615Abstract: A command is issued to reset one or more pending interrupt indicators and arbitrate for ownership of the interrupt. Responsive to a processor receiving the command, a check is made of a selected pending interrupt indicator. If the selected pending interrupt indicator is not set, another pending interrupt indicator is checked, instead of providing a negative response and reissuing the command. In this way, one dequeue command can replace multiple dequeue commands and the overhead of leaving and re-entering the interrupt handler is reduced. A negative response is reserved for those situations in which there are no pending interrupt indicators to be reset.Type: GrantFiled: December 21, 2011Date of Patent: June 24, 2014Assignee: International Business Machines CorporationInventors: Janet R. Easton, Norbert Hagspiel, Bernd Nerz
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Publication number: 20140089621Abstract: According to one aspect of the present disclosure a system and technique for input/output traffic backpressure prediction is disclosed. The system includes a processor unit and logic executable by the processor unit to: determine, for each of a plurality of memory transactions, a traffic value corresponding to a time for performing the respective memory transactions; responsive to determining the traffic value for a respective memory transaction, determine a median value based on the determined traffic values; determine whether successive median values are incrementing; and responsive to a quantity of successively incrementing median values exceeding a threshold, indicate a prediction of a backpressure condition.Type: ApplicationFiled: September 21, 2012Publication date: March 27, 2014Applicant: International Business Machines CorporationInventors: Norbert Hagspiel, Matthias Klein
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Publication number: 20140089607Abstract: According to one aspect of the present disclosure, a method and technique for input/output traffic backpressure prediction is disclosed. The method includes: performing a plurality of memory transactions; determining, for each memory transaction, a traffic value corresponding to a time for performing the respective memory transactions; responsive to determining the traffic value for a respective memory transaction, determining a median value based on the determined traffic values; determining whether successive median values are incrementing; and responsive to a quantity of successively incrementing median values exceeding a threshold, indicating a prediction of a backpressure condition.Type: ApplicationFiled: November 11, 2013Publication date: March 27, 2014Applicant: International Business Machines CorporationInventors: Norbert Hagspiel, Matthias Klein
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Publication number: 20140025922Abstract: An aspect includes a method for operating on translation look-aside buffers (TLBs) in a multiprocessor environment including a plurality of logical partitions as zones. The method includes concurrently receiving a first quiesce request from a first processor of a first zone to quiesce processors of a first set of zones including the first zone and receiving a second quiesce request from a second processor of a second zone to quiesce processors of a second set of zones including the second zone. The second set of zones consists of separate zones from the first set of zones. Based on receiving the first quiesce request, only processors of the first set of zones are quiesced. Based on the processors of the first set of zones being quiesced, a first operation is performed on the TLBs. Based on the first operation being performed, the processors of the first set of zones are un-quiesced.Type: ApplicationFiled: September 24, 2013Publication date: January 23, 2014Applicant: International Business Machines CorporationInventors: Lisa C. Heller, Norbert Hagspiel, Ute Gaertner, Hanno Ulrich, Rebecca S. Wisniewski
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Patent number: 8572624Abstract: A system, method and computer program product for providing multiple quiesce state machines. The system includes a first controller including logic for processing a first quiesce request. The system also includes a second controller including logic for processing a second quiesce request. All or a portion of the processing of the second quiesce request overlaps in time with the processing of the first quiesce request. Thus, multiple quiesce requests may be active in the system at the same time.Type: GrantFiled: February 26, 2008Date of Patent: October 29, 2013Assignee: International Business Machines CorporationInventors: Lisa C. Heller, Norbert Hagspiel, Ute Gaertner, Hanno Ulrich, Rebecca S. Wisniewski
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Publication number: 20130166803Abstract: A command is issued to reset one or more pending interrupt indicators and arbitrate for ownership of the interrupt. Responsive to a processor receiving the command, a check is made of a selected pending interrupt indicator. If the selected pending interrupt indicator is not set, another pending interrupt indicator is checked, instead of providing a negative response and reissuing the command. In this way, one dequeue command can replace multiple dequeue commands and the overhead of leaving and re-entering the interrupt handler is reduced. A negative response is reserved for those situations in which there are no pending interrupt indicators to be reset.Type: ApplicationFiled: December 21, 2011Publication date: June 27, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Janet R. Easton, Norbert Hagspiel, Bernd Nerz
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Patent number: 8166239Abstract: A program product, a translation lookaside buffer and a related method for operating the TLB is provided.Type: GrantFiled: June 20, 2008Date of Patent: April 24, 2012Assignee: International Business Machines CorporationInventors: Matthias Fertig, Ute Gaertner, Norbert Hagspiel, Erwin Pfeffer
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Publication number: 20110320743Abstract: A system and computer implemented method for storing of data in the memory of a computer system in order at a fast rate is provided. The method includes launching a first store to memory. A wait counter is initiated. A second store to memory is speculatively launched when the wait counter expires. The second store to memory is cancelled when the second store achieves coherency prior to the first store to memory.Type: ApplicationFiled: June 24, 2010Publication date: December 29, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Norbert Hagspiel, Matthias Klein, Ulrich Mayer, Robert J. Sonnelitter, III, Gary E. Strait, Hanno Ulrich
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Patent number: 7930514Abstract: A method, system, and computer program product for implementing a dual-addressable cache is provided. The method includes adding fields for indirect indices to each congruence class provided in a cache directory. The cache directory is indexed by primary addresses. In response to a request for a primary address based upon a known secondary address corresponding to the primary address, the method also includes generating an index for the secondary address, and inserting or updating one of the indirect indices into one of the fields for a congruence class relating to the secondary address. The indirect index is assigned a value of a virtual index corresponding to the primary address. The method further includes searching congruence classes of each of the indirect indices for the secondary address.Type: GrantFiled: February 9, 2005Date of Patent: April 19, 2011Assignee: International Business Machines CorporationInventors: Norbert Hagspiel, Erwin Pfeffer, Bruce A. Wagar
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Patent number: 7650535Abstract: Detecting and correcting errors in arrays after ABIST testing, after ABIST testing, detected errors are faults are isolated by blowing a fuse.Type: GrantFiled: September 16, 2006Date of Patent: January 19, 2010Assignee: International Business Machines CorporationInventors: Norbert Hagspiel, William V. Huott, Frank Lehnert, Brian R. Prasky, Richard Rizzolo, Rolf Sautter
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Publication number: 20090217269Abstract: A system, method and computer program product for providing multiple quiesce state machines. The system includes a first controller including logic for processing a first quiesce request. The system also includes a second controller including logic for processing a second quiesce request. All or a portion of the processing of the second quiesce request overlaps in time with the processing of the first quiesce request. Thus, multiple quiesce requests may be active in the system at the same time.Type: ApplicationFiled: February 26, 2008Publication date: August 27, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lisa C. Heller, Norbert Hagspiel, Ute Gaertner, Hanno Ulrich, Rebecca S. Wisniewski
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Publication number: 20080320216Abstract: A program product, a translation lookaside buffer and a related method for operating the TLB is provided.Type: ApplicationFiled: June 20, 2008Publication date: December 25, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthias Fertig, Ute Gaertner, Norbert Hagspiel, Erwin Pfeffer
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Publication number: 20080126900Abstract: Detecting and correcting errors in arrays after ABIST testing, after ABIST testing, detected errors are faults are isolated by blowing a fuse.Type: ApplicationFiled: September 16, 2006Publication date: May 29, 2008Inventors: Norbert Hagspiel, William V. Huott, Frank Lehnert, Brian R. Prasky, Richard Rizzolo, Rolf Sauter
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Publication number: 20060179233Abstract: A method, system, and computer program product for implementing a dual-addressable cache is provided. The method includes adding fields for indirect indices to each congruence class provided in a cache directory. The cache directory is indexed by primary addresses. In response to a request for a primary address based upon a known secondary address corresponding to the primary address, the method also includes generating an index for the secondary address, and inserting or updating one of the indirect indices into one of the fields for a congruence class relating to the secondary address. The indirect index is assigned a value of a virtual index corresponding to the primary address. The method further includes searching congruence classes of each of the indirect indices for the secondary address.Type: ApplicationFiled: February 9, 2005Publication date: August 10, 2006Applicant: International Business Machines CorporationInventors: Norbert Hagspiel, Erwin Pfeffer, Bruce Wagar
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Patent number: 6766434Abstract: The present invention generally relates to shared-memory multiprocessor systems, such as IBM ESA/390 or RS/6000 systems, and deals more particularly with a method and system for sharing a second-level translation lookaside buffer (TLB 2) between several CPUs (30a, . . . 30d) for improving the performance and reducing the chip area required to buffer the results of virtual-to-absolute address translations. The inventive TLB2 organization comprises several small arrays (32a, . . . 32d) dedicated to particular CPUs, providing an interface to a major array (21), which is shared between the CPUs. The dedicated arrays 32a, . . . 32d) are required to fulfill the architected constraints and link several CPUs to the commonly used shared array (21).Type: GrantFiled: April 19, 2002Date of Patent: July 20, 2004Assignee: International Business Machines CorporationInventors: Ute Gaertner, Norbert Hagspiel, Frank Lehnert, Erwin Pfeffer, Kerstin Schelm
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Patent number: 6654669Abstract: A processor unit for a data-processing-aided electronic control system in a motor vehicle, in which the processor unit operates in real-time and contains within its functional structure a scalable computing unit and a vehicle interface unit, as well as (preferably) a communication coprocessor as separate structural components.Type: GrantFiled: November 16, 1998Date of Patent: November 25, 2003Assignees: DaimlerChrysler AG, International Business Machines CorporationInventors: Joachim Eisenmann, Stefan Gleissner, Philipp Lanches, Markus Mrossko, Hans-Juergen Aminger, Wolfgang Eibach, Volkmar Goetze, Matthias Gruetzner, Norbert Hagspiel, Matthias Koehn, Martin Neumann, Reiner Rieke, Dieter Staiger
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Publication number: 20020156989Abstract: The present invention generally relates to shared-memory multiprocessor systems, such as IBM ESA/390 or RS/6000 systems, and deals more particularly with a method and system for sharing a second-level translation lookaside buffer (TLB 2) between several CPUs (30a, . . . 30d) for improving the performance and reducing the chip area required to buffer the results of virtual-to-absolute address translations. The inventive TLB2 organization comprises several small arrays (32a, . . . 32d) dedicated to particular CPUs, providing an interface to a major array (21), which is shared between the CPUs. The dedicated arrays 32a, . . . 32d) are required to fulfill the architected constraints and link several CPUs to the commonly used shared array (21).Type: ApplicationFiled: April 19, 2002Publication date: October 24, 2002Applicant: International Business Machines CorporationInventors: Ute Gaertner, Norbert Hagspiel, Frank Lehnert, Erwin Pfeffer, Kerstin Schelm
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Publication number: 20010002449Abstract: A processor unit for a data-processing-aided electronic control system in a motor vehicle, in which the processor unit operates in real-time and contains within its functional structure a scalable computing unit and a vehicle interface unit, as well as (preferably) a communication coprocessor as separate structural components.Type: ApplicationFiled: November 16, 1998Publication date: May 31, 2001Applicant: DAIMLER-BENZ AKTIENGESELLSCHAFT AND INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: JOACHIM EISENMANN, STEFAN GLEISSNER, PHILIPP LANCHES, MARKUS MROSSKO, HANS-JUERGEN AMINGER, WOLFGANG EIBACH, VOLKMAR GOETZE, MATTHIAS GRUETZNER, NORBERT HAGSPIEL, MATTHIAS KOEHN, MARTIN NEUMANN, REINER RIEKE, DIETER STAIGER