Abstract: The present invention relates to a process for purifying C1-esterase inhibitor (C1-Inh), and more in particular a Cl-Inh concentrate.

Abstract: A semiconductor memory having charge trapping memory cells and fabrication method thereof. The direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.

Abstract: A semiconductor memory having charge trapping memory cells and fabrication method thereof. The direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.

Abstract: A semiconductor memory having charge trapping memory cells, where the direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.

Abstract: A non-volatile semiconductor memory includes a substrate having a substrate region, at least one word line, a plurality of non-volatile memory cells arranged in a plurality of sectors and further comprising first wells of a first doping type, electrically insulating elements and switching elements. Each sector includes a plurality of non-volatile memory cells commonly arranged in a respective first well. The at least one word line electrically connecting memory cells of a group of sectors among the plurality of sectors. The first wells are separated from the substrate region and from each other by means of the electrically insulating elements. Each first well is connected to a respective switching element and the semiconductor memory is constructed such that each first well is biasable to a predetermined potential by means of the respective switching element. Further, a method is provided for operating the above non-volatile semiconductor memory.

Abstract: A semiconductor memory having charge trapping memory cells, where the direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.

Abstract: A non-volatile semiconductor memory includes a substrate having a substrate region, at least one word line, a plurality of non-volatile memory cells arranged in a plurality of sectors and further comprising first wells of a first doping type, electrically insulating elements and switching elements. Each sector comprises a plurality of non-volatile memory cells commonly arranged in a respective first well. The at least one word line electrically connecting memory cells of a group of sectors among the plurality of sectors. The first wells are separated from the substrate region and from each other by means of the electrically insulating elements. Each first well is connected to a respective switching element and the semiconductor memory is constructed such that each first well is biasable to a predetermined potential by means of the respective switching element. Further, a method is provided for operating the above non-volatile semiconductor memory.

Abstract: A method for fabricating a drain/source path is provided, in which essentially firstly a nitride layer is applied, on which a TEOS layer is then patterned. The patterning is effected in a simplified manner by virtue of the fact that the nitride layer acts as an etching stop layer during the etching away of the TEOS layer.

Abstract: The invention relates to a process for producing erythropoietin (EPO) in which eukaryotic cells, which are suitable for expressing EPO, are adapted to SMIF7 medium in a suitable bioreactor, the resulting cells are transferred to a larger bioreactor and further expanded with SMIF7 medium and, while constantly bleeding and constantly perfusing, the expressed EPO is isolated from the larger bioreactor and purified.