Abstract: A latch is provided that includes a first inverter, a second inverter, a first latch circuit and a second latch circuit. The first inverter to receive the first clock signal from an input port and to provide a clock signal. The second inverter to receive the first clock signal from the input port and to provide a clock signal. The first latch circuit is to store data and to receive a clock signal from the second inverter. The second latch circuit is further to store data and to receive a clock signal from the first inverter.

Abstract: A latch is provided that includes a first inverter, a second inverter, a first latch circuit and a second latch circuit. The first inverter to receive the first clock signal from an input port and to provide a clock signal. The second inverter to receive the first clock signal from the input port and to provide a clock signal. The first latch circuit is to store data and to receive a clock signal from the second inverter. The second latch circuit is further to store data and to receive a clock signal from the first inverter.

Abstract: An apparatus including a plurality of semiconductor devices coupled via a plurality of circuit paths to store information. Selected circuit paths of the plurality of circuit paths present increased resistance, the increased resistance being sufficient to cooperate with capacitance present in the apparatus to establish a resistive-capacitive (RC) time constant in the selected circuit paths. The RC time constant being appropriate to accommodate a noise signal having a predetermined duration without the apparatus losing stored information.

Abstract: A method and apparatus for reducing soft errors is disclosed. In some embodiments the method comprises: assigning a plurality of nodes within a storage circuit to a predetermined state; evaluating a plurality of signals coupled to the storage circuit, where evaluating the plurality of signals enables a first node to change from its predetermined state and enables a second node to be more susceptible to perturbations; and maintaining the second node in its predetermined state for a predetermined period of time, where maintaining the predetermined state reduces the storage circuit's susceptibility to soft errors.

Abstract: Methods are disclosed for calculating the amount of voltage coupled to a device. In some embodiments, the method may comprise identifying a conductor that is coupled to a device, extracting information regarding the relationship between the conductor coupled to the device and adjacent conductors, extracting information regarding signals that are present in the adjacent conductors, partitioning the signal information into phases, calculating a voltage induced in the conductor coupled to the device during each phase of the partitioned signal, calculating an average voltage induced in the conductor coupled to the device and, flagging the device if the average voltage induced is above a predetermined threshold.