Abstract: To record the address of a storage cell that has contents that are erroneous with respect to the coding, a memory configuration, connected by means of a bus line system with a central control unit, is equipped with a register in the recording cells of which can be written the address of the selected storage cell which is transmitted over the bus line system during the performance of a read cycle in the memory's configuration. Each memory contents that are read out from one of the storage cells in the course of such a read cycle are checked in an error-recognition circuit for the existence of a coding error. When a coding error of this kind is recognized, the error recognition circuit then emits an appropriate error signal. In response to such an error signal, a control device locks out the register for the reception of another address transmitted over the bus line system.

Abstract: A central control unit that is connected with a number of circuit assemblies and has two interrupt inputs. Of these interrupt inputs, at first, when the circuit assemblies are in a fault-free state, only the one with the lower interrupt priority is activated. A register is provided, into which, when the circuit assemblies are driven by the central control unit, data with regard to the precise circuit assembly that is being driven in each case can be written. In addition, there is provided at least one fault recognition circuit, which when a fault exists in the respective circuit assembly, emits a fault signal when that assembly is driven. Connected with the abovementioned interrupt inputs is a control device, which, in response to such a fault signal, effects, through the activated interrupt input, the performance of a first interrupt routine, in the course of which the interrupt input with the higher interrupt priority is activated.