Abstract: An amplification unit reduces a duty cycle of a digital signal at a carrier radio frequency to optimize the efficiency of the RF power amplifier that amplifies the reduced duty cycle signal. An exemplary amplification unit includes a duty cycle controller and a digital power amplifier. A delay unit in the duty cycle controller applies a delay to an input digital signal at the carrier radio frequency to generate a delayed signal at the carrier radio frequency. A logic gate in the duty cycle controller logically combines the input digital signal with the delayed signal to generate a modified digital signal at the carrier radio frequency, where the modified input digital signal has a reduced duty cycle relative to that of the input digital signal. Amplifying the modified digital signal in the digital RF power amplifier generates an amplified analog signal at the carrier radio frequency while improving amplifier efficiency.

Abstract: A polar modulation power amplifier employs both thermometer coded and binary coded amplitude modulation data. The thermometer coded amplitude modulation data selectively activates one or more equally weighted power amplifier cells. The binary coded amplitude modulation data selectively activates one or more binary weighted power amplifier cells. When less than full output power is required and the MSBs of the amplitude modulation data are zero (reducing output power at the expense of quantization noise), the power dissipated by RF signal buffers for the unused power amplifier cells corresponding to the MSBs is substantially reduced by gating off the RF signal upstream of the buffers.

Abstract: A current mirror circuit exhibits improved current matching by applying a switching signal to ground path switches in series with transistors in both a reference path and an output path of the current mirror. The switching signal may comprise a high-frequency signal, which may be phase modulated. A plurality of matched, parallel-connected output transistors may be selectively enabled by qualifying the switching signal applied to each corresponding series-connected ground path switches by decoded digital modulation data. In one embodiment, the modulation data is decoded to thermometer-coded representation. In one embodiment, the switching signal path is identical to the reference and output circuits.

Abstract: An on-chip power amplifier includes first and second variable capacitors connected in parallel with first and second windings, respectively, of an on-chip balun. The first balun winding connects between the differential outputs of an on-chip differential amplifier. Varying the first variable capacitor changes the imaginary part of the load impedance of the differential amplifier, while varying the second variable capacitor changes the real part of the load impedance of the differential amplifier. In one embodiment, the first and second variable capacitors are generally orthogonal, such that the first and second variable capacitors are less than 25% correlated. As a result, varying the first variable capacitor has little impact on the real part of the load impedance, and varying the second variable capacitor has little impact on the imaginary part of the load impedance. In this way the load impedance can be tuned to the optimum performance.

Abstract: A calibration unit calibrates a power amplifier load impedance to achieve a nominal amplifier load impedance after the connection of one or more external elements, e.g., antenna, to improve the accuracy and effectiveness of output power calibration. The calibration unit comprises an adaptive impedance unit and a controller. The adaptive impedance unit includes first and second variable impedance elements connected between the amplifier and the external load, e.g., antenna. The controller independently calibrates the imaginary and real parts of the load impedance by respectively selecting first and second calibration values for the first and second variable impedance elements based on a reference voltage. More particularly, the controller selects calibration values for the first and second variable impedance elements from a plurality of impedance values based on a comparison between a reference voltage and the calibrated voltages produced at the output of the power amplifier responsive to the impedance values.

Abstract: A current mirror circuit exhibits improved current matching by applying a switching signal to ground path switches in series with transistors in both a reference path and an output path of the current mirror. The switching signal may comprise a high-frequency signal, which may be phase modulated. A plurality of matched, parallel-connected output transistors may be selectively enabled by qualifying the switching signal applied to each corresponding series-connected ground path switches by decoded digital modulation data. In one embodiment, the modulation data is decoded to thermometer-coded representation. In one embodiment, the switching signal path is identical to the reference and output circuits.

Abstract: A polar modulation power amplifier employs both thermometer coded and binary coded amplitude modulation data. The thermometer coded amplitude modulation data selectively activates one or more equally weighted power amplifier cells. The binary coded amplitude modulation data selectively activates one or more binary weighted power amplifier cells. When less than full output power is required and the MSBs of the amplitude modulation data are zero (reducing output power at the expense of quantization noise), the power dissipated by RF signal buffers for the unused power amplifier cells corresponding to the MSBs is substantially reduced by gating off the RF signal upstream of the buffers.

Abstract: An amplification unit reduces a duty cycle of a digital signal at a carrier radio frequency to optimize the efficiency of the RF power amplifier that amplifies the reduced duty cycle signal. An exemplary amplification unit includes a duty cycle controller and a digital power amplifier. A delay unit in the duty cycle controller applies a delay to an input digital signal at the carrier radio frequency to generate a delayed signal at the carrier radio frequency. A logic gate in the duty cycle controller logically combines the input digital signal with the delayed signal to generate a modified digital signal at the carrier radio frequency, where the modified input digital signal has a reduced duty cycle relative to that of the input digital signal. Amplifying the modified digital signal in the digital RF power amplifier generates an amplified analog signal at the carrier radio frequency while improving amplifier efficiency.

Abstract: An on-chip power amplifier includes first and second variable capacitors connected in parallel with first and second windings, respectively, of an on-chip balun. The first balun winding connects between the differential outputs of an on-chip differential amplifier. Varying the first variable capacitor changes the imaginary part of the load impedance of the differential amplifier, while varying the second variable capacitor changes the real part of the load impedance of the differential amplifier. In one embodiment, the first and second variable capacitors are generally orthogonal, such that the first and second variable capacitors are less than 25% correlated. As a result, varying the first variable capacitor has little impact on the real part of the load impedance, and varying the second variable capacitor has little impact on the imaginary part of the load impedance. In this way the load impedance can be tuned to the optimum performance.

Abstract: A calibration unit calibrates a power amplifier load impedance to achieve a nominal amplifier load impedance after the connection of one or more external elements, e.g., antenna, to improve the accuracy and effectiveness of output power calibration. The calibration unit comprises an adaptive impedance unit and a controller. The adaptive impedance unit includes first and second variable impedance elements connected between the amplifier and the external load, e.g., antenna. The controller independently calibrates the imaginary and real parts of the load impedance by respectively selecting first and second calibration values for the first and second variable impedance elements based on a reference voltage. More particularly, the controller selects calibration values for the first and second variable impedance elements from a plurality of impedance values based on a comparison between a reference voltage and the calibrated voltages produced at the output of the power amplifier responsive to the impedance values.