Abstract: The asymmetrical non-volatile memory cell is provided on a substrate of first conductivity type and comprises a control region and a floating region, wherein the control region is adjacent to the floating region and isolated from the floating region. The control region further comprises an implant region, having second conductivity type, disposed entirely across the control region and a polycrystalline silicon control gate disposed entirely over the implant region. The floating region further comprises a first voltage state of a drain implant region and a second voltage state of a source implant region, both having second conductivity type, the first voltage state is different from the second voltage state, a channel region that separates the drain implant region and the source implant region, and a polycrystalline silicon floating gate disposed entirely over the channel region and at least partially over the source implant region and drain implant region.