Patents by Inventor Noriaki Maeda
Noriaki Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170309327Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.Type: ApplicationFiled: July 13, 2017Publication date: October 26, 2017Inventors: Shigenobu KOMATSU, Masanao YAMAOKA, Noriaki MAEDA, Masao MORIMOTO, Yasuhisa SHIMAZAKI, Yasuyuki OKUMA, Toshiaki SANO
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Publication number: 20170271344Abstract: A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions.Type: ApplicationFiled: June 7, 2017Publication date: September 21, 2017Inventors: Masao MORIMOTO, Noriaki MAEDA, Yasuhisa SHIMAZAKI
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Publication number: 20170253152Abstract: A method of producing a seat reclining apparatus includes connecting one of a first connecting portion and a second connecting portion of a biasing member to associated one of a base member and a lock drive member, with a lock member and the lock drive member supported on the base member, thereby bringing the biasing member to a temporarily held state; mounting the ratchet to the base member so as to cover the biasing member in the temporarily held state; and fixing the other of the first connecting portion and the second connecting portion to the other of the base member and the lock drive member through an opening which is formed in one of the base member and the ratchet, thereby bringing the biasing member to the biasing state from the temporarily held state.Type: ApplicationFiled: February 24, 2017Publication date: September 7, 2017Applicant: SHIROKI CORPORATIONInventors: Noriaki MAEDA, HIDEHIKO FUJIOKA
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Publication number: 20170253151Abstract: A seat reclining apparatus includes a base member and a ratchet on a seat cushion and a seatback, respectively or vice versa; a lock member which engages with and disengages from a meshing portion of the ratchet; a lock driver which moves the lock member between the engaged position and the disengaged position; and a meshed-state retainer including an engaging portion provided on the base member, and an engaged portion provided on the lock member. When the lock member in the engaged position moves in a direction different from a direction in which the lock member is guided by the guide portion of the base member, the meshed-state retainer moves the lock member toward the engaged position via engagement of the engaged portion with the engaging portion to retain a meshed state between the lock member and the meshing portion of the ratchet.Type: ApplicationFiled: February 24, 2017Publication date: September 7, 2017Applicant: SHIROKI CORPORATIONInventors: Noriaki MAEDA, Hidehiko FUJIOKA
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Patent number: 9734893Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.Type: GrantFiled: February 22, 2016Date of Patent: August 15, 2017Assignee: Renesas Electronics CorporationInventors: Shigenobu Komatsu, Masanao Yamaoka, Noriaki Maeda, Masao Morimoto, Yasuhisa Shimazaki, Yasuyuki Okuma, Toshiaki Sano
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Patent number: 9704873Abstract: A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions.Type: GrantFiled: May 26, 2016Date of Patent: July 11, 2017Assignee: Renesas Electronics CorporationInventors: Masao Morimoto, Noriaki Maeda, Yasuhisa Shimazaki
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Patent number: 9630529Abstract: A seat reclining apparatus is provided in which a spring cover which covers a lock spring for rotationally biasing a rotational cam can be easily and securely mounted to an outer surface of a base plate or a ratchet plate. The seat reclining apparatus is provided with a lock spring disposed to face the outer surface of the base plate or disposed in a hole in the base plate to bias and rotate the rotational center shaft in a direction to rotate the rotational cam toward the locked position, and a spring cover disposed to face the outer surface of the base plate and covers the lock spring, and to make an inner surface of one of the seat cushion side frame and the seatback side frame contact an outer surface of a protrusion which is projected from the spring cover.Type: GrantFiled: July 17, 2013Date of Patent: April 25, 2017Assignee: SHIROKI CORPORATIONInventors: Nobumasa Higashi, Noriaki Maeda, Kazutaka Sasaki
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Publication number: 20170092352Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.Type: ApplicationFiled: December 9, 2016Publication date: March 30, 2017Inventors: Toshiaki SANO, Ken SHIBATA, Shinji TANAKA, Makoto YABUUCHI, Noriaki MAEDA
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Publication number: 20170037945Abstract: A reclining device includes: a first member; a pawl having external teeth; a second member; a cam; and a spring, which biases the cam to move the pawl in the direction where the external teeth engage with the internal teeth, the pawl guide includes a first pawl guide and a second pawl guide, a wedge-shaped space is formed between the pawl and the first pawl guide, and a width of the wedge-shaped space is gradually reduced in a direction where the pawl is guided, an end of the spring is inserted into the wedge-shaped space, and the end of the spring is directly wedged into the wedge-shaped space, thereby pressing the pawl against the second pawl guide.Type: ApplicationFiled: August 2, 2016Publication date: February 9, 2017Inventors: Noriaki MAEDA, Hidehiko FUJIOKA
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Patent number: 9548106Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.Type: GrantFiled: April 21, 2016Date of Patent: January 17, 2017Assignee: Renesas Electronics CorporationInventors: Toshiaki Sano, Ken Shibata, Shinji Tanaka, Makoto Yabuuchi, Noriaki Maeda
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Patent number: 9452696Abstract: A seat reclining apparatus includes a base plate, a ratchet plate, a lock member guided by a guide groove of the base plate between engaged and disengaged positions, a first cam between the base plate and the ratchet plate, and a second cam which moves toward and presses the lock member to an engaged position by the first cam when the first cam rotates from the unlocked to locked positions. The second cam includes a surface contact portion which comes in surface contact with a guide surface in the guide groove, an engaging portion which is pressed by the first cam, and a pressing portion which presses a pressed portion of the lock member. One and the other of the pressing portion and the pressed portion respectively includes a flat surface and a curved surface that is convex toward the flat surface.Type: GrantFiled: September 17, 2013Date of Patent: September 27, 2016Assignee: Shiroki CorporationInventors: Nobumasa Higashi, Noriaki Maeda, Kazutaka Sasaki
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Publication number: 20160276352Abstract: A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions.Type: ApplicationFiled: May 26, 2016Publication date: September 22, 2016Inventors: Masao MORIMOTO, Noriaki MAEDA, Yasuhisa SHIMAZAKI
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Publication number: 20160240246Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.Type: ApplicationFiled: April 21, 2016Publication date: August 18, 2016Inventors: Toshiaki SANO, Ken SHIBATA, Shinji TANAKA, Makoto YABUUCHI, Noriaki MAEDA
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Patent number: 9385133Abstract: A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions.Type: GrantFiled: October 23, 2015Date of Patent: July 5, 2016Assignee: Renesas Electronics CorporationInventors: Masao Morimoto, Noriaki Maeda, Yasuhisa Shimazaki
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Publication number: 20160172022Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.Type: ApplicationFiled: February 22, 2016Publication date: June 16, 2016Inventors: Shigenobu KOMATSU, Masanao YAMAOKA, Noriaki MAEDA, Masao MORIMOTO, Yasuhisa SHIMAZAKI, Yasuyuki OKUMA, Toshiaki SANO
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Patent number: 9368194Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.Type: GrantFiled: April 21, 2015Date of Patent: June 14, 2016Assignee: Renesas Electronics CorporationInventors: Shigenobu Komatsu, Masanao Yamaoka, Noriaki Maeda, Masao Morimoto, Yasuhisa Shimazaki, Yasuyuki Okuma, Toshiaki Sano
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Patent number: 9349438Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.Type: GrantFiled: March 14, 2015Date of Patent: May 24, 2016Assignee: Renesas Electronics CorporationInventors: Toshiaki Sano, Ken Shibata, Shinji Tanaka, Makoto Yabuuchi, Noriaki Maeda
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Patent number: 9320358Abstract: A seat reclining apparatus includes a first and second plates and a lock mechanism which locks/unlocks relative rotation therebetween. The first plate includes an engaging protrusion on a side engaged in a holding portion, and a protrusion-corresponding recess formed on the other side of the first plate recessed at a position corresponding to the engaging protrusion. The engaging protrusion includes a pressure receiving portion on a peripheral edge thereof and engages with an inner peripheral surface of the holding portion to receive a force therefrom when a load is exerted on a seatback frame in the locked state. The first plate includes an annular bridging portion connecting the peripheral edges of the engaging protrusion and the protrusion-corresponding recess; the annular bridging portion including a thin-wall portion, and a thick-wall portion corresponding to the pressure receiving portion.Type: GrantFiled: September 30, 2013Date of Patent: April 26, 2016Assignee: SHIROKI CORPORATIONInventor: Noriaki Maeda
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Publication number: 20160043091Abstract: A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions.Type: ApplicationFiled: October 23, 2015Publication date: February 11, 2016Inventors: Masao Morimoto, Noriaki Maeda, Yasuhisa Shimazaki
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Publication number: 20150380076Abstract: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.Type: ApplicationFiled: August 25, 2015Publication date: December 31, 2015Inventors: Noriaki MAEDA, Yoshihiro SHINOZAKI, Masanao YAMAOKA, Yasuhisa SHIMAZAKI, Masanori ISODA, Koji NII