Patents by Inventor Noriaki Minamida
Noriaki Minamida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8654696Abstract: A base station realizing enhancement of the interpolation accuracy of the channel estimate between sub-frames. In a base station (100), a scrambling section (105) carries out scrambling such that a predetermined pilot signal sequence is multiplied by a scrambling sequence containing both a sequence unique to the base station (100) and different with cells and a sequence common to base stations for each chip and generates a pilot sequence containing both a pilot for unicast sub-frame and a pilot for multicast sub-frame, a multiplexing section (106) for time-multiplexing the pilot sequence, the unicast data symbol, and a multicast data symbol for each sub-frame, and an S/P section (107) converts the pilot sequences, the unicast data symbols, and the multicast data symbols sequential serially inputted from the multiplexing section (106) the numbers of which are equal to the number of subcarries included in one OFDM symbol into parallel ones and outputs them to an IFFT section (108).Type: GrantFiled: October 6, 2006Date of Patent: February 18, 2014Assignee: Panasonic CorporationInventors: Masaru Fukuoka, Akihiko Nishio, Noriaki Minamida
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Patent number: 7634291Abstract: A communication terminal apparatus wherein even in a case of occurrence of a compressed mode, an evaluation can be performed by a detecting function to select an appropriate TFC (TRANS Format Combination). In this communication terminal apparatus, upon occurrence of a compressed mode, a compressed mode information generating part (173) outputs both a gap section and a gap start slot number for application to a transmission power determining part (174), which then counts the slots in which the TFC transmission power exceeds an upper limit for each TFC. At this moment, the transmission power determining part (174) replaces the TFC transmission power, for the slots of the gap section, by the TFC transmission power of the slots other than those of the gap section. ATFC status managing part (175) determines, based on the counting result of the transmission power determining part (174), the status of each TFC.Type: GrantFiled: June 21, 2005Date of Patent: December 15, 2009Assignee: Panasonic CorporationInventors: Ryutaro Yamanaka, Noriaki Minamida
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Publication number: 20090190516Abstract: A base station realizing enhancement of the interpolation accuracy of the channel estimate between sub-frames. In a base station (100), a scrambling section (105) carries out scrambling such that a predetermined pilot signal sequence is multiplied by a scrambling sequence containing both a sequence unique to the base station (100) and different with cells and a sequence common to base stations for each chip and generates a pilot sequence containing both a pilot for unicast sub-frame and a pilot for multicast sub-frame, a multiplexing section (106) for time-multiplexing the pilot sequence, the unicast data symbol, and a multicast data symbol for each sub-frame, and an S/P section (107) converts the pilot sequences, the unicast data symbols, and the multicast data symbols sequential serially inputted from the multiplexing section (106) the numbers of which are equal to the number of subcarries included in one OFDM symbol into parallel ones and outputs them to an IFFT section (108).Type: ApplicationFiled: October 6, 2006Publication date: July 30, 2009Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Masaru Fukuoka, Akihiko Nishio, Noriaki Minamida
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Publication number: 20080220802Abstract: A communication terminal apparatus wherein even in a case of occurrence of a compressed mode, an evaluation can be performed by a detecting function to select an appropriate TFC (TRANS Format Combination). In this communication terminal apparatus, upon occurrence of a compressed mode, a compressed mode information generating part (173) outputs both a gap section and a gap start slot number for application to a transmission power determining part (174), which then counts the slots in which the TFC transmission power exceeds an upper limit for each TFC. At this moment, the transmission power determining part (174) replaces the TFC transmission power, for the slots of the gap section, by the TFC transmission power of the slots other than those of the gap section. ATFC status managing part (175) determines, based on the counting result of the transmission power determining part (174), the status of each TFC.Type: ApplicationFiled: June 21, 2005Publication date: September 11, 2008Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Ryutaro Yamanaka, Noriaki Minamida
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Publication number: 20050202812Abstract: A mobile apparatus that can perform roaming without being provided with a region preset table storing usable frequency information and so forth for each area. A service information provision apparatus that provides this mobile apparatus with various kinds of information necessary when roaming is performed. A roaming method associated with the movement of this mobile apparatus.Type: ApplicationFiled: March 23, 2004Publication date: September 15, 2005Inventors: Noriaki Minamida, Masatoshi Watanabe
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Patent number: 6907009Abstract: In the equation for obtaining the number of increase or decrease bits Zij on each channel for each frame defined in the specification TS25.212 Ver.3.1.0 of 3GPP that is a standard organization of the 3rd generation digital mobile communication, Ndataj is multiplied by a calculation result of RMm*Nmj/RMm*Nmj. According to a rate matching calculation method of the present invention, the correction value 1/N2dataj is added in order to prevent the added whole value of the equation from exceeding 1 when Ndataj is multiplied.Type: GrantFiled: March 30, 2001Date of Patent: June 14, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yasuyo Maruwaka, Noriaki Minamida
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Publication number: 20040202114Abstract: In the equation for obtaining the number of increase or decrease bits Zij on each channel for each frame defined in the specification TS25.212 Ver.3.1.0 of 3GPP that is a standard organization of the 3rd generation digital mobile communication, Ndataj is multiplied by a calculation result of RMm*Nmj/RMm*Nmj. According to a rate matching calculation method of the present invention, the correction value 1/N2dataj is added in order to prevent the added whole value of the equation from exceeding 1 when Ndataj is multiplied.Type: ApplicationFiled: May 6, 2004Publication date: October 14, 2004Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Yasuyo Maruwaka, Noriaki Minamida
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Patent number: 6637001Abstract: Voice coding section 101 generates voice data and image coding section 102 generates image data, an error decision bit is added to each of these data and these data are multiplexed and transmitted. On the receiving side, reception section 107 receives this multiplexed data, separation section 108 separates the multiplexed data into the voice data and image data. This voice data and image data are subjected to transmission error decision by voice reception code error decision section 109 and image reception code error decision section 110, respectively. Then, voice decoding section 111 decodes the voice data and image decoding section 112 decodes the image data.Type: GrantFiled: August 30, 2000Date of Patent: October 21, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Noriaki Minamida
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Publication number: 20020122557Abstract: A first-stage processing section 105 detects a plurality of slot timings corresponding to a plurality of correlation values equal to or greater than a threshold value, a second-stage processing section 110 detects scrambling code timing and a scrambling code group in accordance with one of the slot timings, a third-stage processing section 115 identifies a scrambling code in accordance with the scrambling code timing, and a controller 104 switches a switch 103 so that processing by the second-stage processing section 110 and processing by the third-stage processing section 115 are executed for a plurality of slot timings each time processing by the first-stage processing section 105 is executed once.Type: ApplicationFiled: February 7, 2002Publication date: September 5, 2002Inventors: Koichi Aihara, Junji Somon, Satoshi Imaizumi, Noriaki Minamida, Hidetoshi Suzuki
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Publication number: 20010046211Abstract: In the equation for obtaining the number of increase or decrease bits Zij on each channel for each frame defined in the specification TS25.212 Ver.3.1.0 of 3GPP that is a standard organization of the 3rd generation digital mobile communication, Ndataj is multiplied by a calculation result of RMm*Nmj/RMm*Nmj. According to a rate matching calculation method of the present invention, the correction value 1/N2dataj is added in order to prevent the added whole value of the equation from exceeding 1 when Ndataj is multiplied.Type: ApplicationFiled: March 30, 2001Publication date: November 29, 2001Inventors: Yasuyo Maruwaka, Noriaki Minamida
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Patent number: 6256513Abstract: In a multimedia radio communication system in which a plurality of types of information media are combined, more than two terminals are connected to one terminal interface adapter connected to a mobile station apparatus. In this way, more than two sorts of information are multiplexed and communicated by radio between one mobile station and a base station.Type: GrantFiled: July 17, 1998Date of Patent: July 3, 2001Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Noriaki Minamida
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Patent number: 5517439Abstract: An arithmetic unit includes an arithmetic and logic circuit having n bits and capable of controlling the execution of either addition or subtraction by responding to a signal indicative of a positive or negative sign of a result of one preceding calculation, a register of n bits for temporarily storing data delivered out of the arithmetic and logic circuit, a register of n bits for delivering a divisor to the arithmetic and logic circuit, a shift register of n stages for sequentially storing signals indicative of a positive or negative sign of results of calculation by the arithmetic and logic circuit, and a shifter for shifting data of the register by one bit to the left and inserting data of the most significant bit of the shift register into the least significant bit to provide an output which in turn is delivered to the arithmetic and logic circuit. A conventional shifter having a bit length of 2n can be replaced with the shifter having a bit length of n and the shift register having a bit length of n.Type: GrantFiled: February 2, 1995Date of Patent: May 14, 1996Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hidetoshi Suzuki, Toshihiro Ishikawa, Yukihiro Fujimoto, Noriaki Minamida