Patents by Inventor Noriaki MUKAIDE

Noriaki MUKAIDE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device having a plurality of transistors connected in parallel
    Patent number: 9806162
    Abstract: A semiconductor device SD includes a substrate SUB, a plurality of gate electrodes GE, a gate pad GEP, and gate interconnects GINC. The plurality of gate electrodes GE are formed in the substrate SUB, and extend electrically in parallel to each other. The gate pad GEP is formed in a region different from that in which the plurality of gate electrodes GE are formed in the substrate SUB. Each of a plurality of gate interconnects GINC connects the plurality of gate electrodes GE to the gate pad GEP.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: October 31, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Kinya Ohtani, Kenji Okada, Yasuhiro Nishimura, Noriaki Mukaide
  • SEMICONDUCTOR DEVICE
    Publication number: 20160027736
    Abstract: A semiconductor device SD includes a substrate SUB, a plurality of gate electrodes GE, a gate pad GEP, and gate interconnects GINC. The plurality of gate electrodes GE are formed in the substrate SUB, and extend electrically in parallel to each other. The gate pad GEP is formed in a region different from that in which the plurality of gate electrodes GE are formed in the substrate SUB. Each of a plurality of gate interconnects GINC connects the plurality of gate electrodes GE to the gate pad GEP.
    Type: Application
    Filed: July 17, 2015
    Publication date: January 28, 2016
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Kinya OHTANI, Kenji OKADA, Yasuhiro NISHIMURA, Noriaki MUKAIDE