Patents by Inventor Noriaki Okumiya

Noriaki Okumiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6445002
    Abstract: In a method for setting appropriate initial-failure screening conditions when mass-producing semiconductor devices of multiple types, devices of each type being manufactured in a small number, the step of subjecting products of every type to an acceleration test is excluded, and instead, the failure ratio on the market of semiconductor devices of each type is estimated using a testing semiconductor device. Specifically, {circle around (1)} first, all types of semiconductor devices to be developed and mass-produced are classified into several groups. {circle around (2)} A test semiconductor device is developed which has the same number of elements, the same gate area, the same multi-layer wiring length and the same number of contact holes as the average number of elements, the average gate area, the average wiring length and the average number of contact holes of the semiconductor devices included in one of the type groups, respectively.
    Type: Grant
    Filed: July 21, 2000
    Date of Patent: September 3, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takehiro Hashimoto, Yutaka Tanaka, Tetsuya Asami, Youichi Satou, Noriaki Okumiya
  • Patent number: 6223097
    Abstract: In a method for setting appropriate initial-failure screening conditions when mass-producing semiconductor devices of multiple types, devices of each type being manufactured in a small number, the step of subjecting products of every type to an acceleration test is excluded, and instead, the failure ratio on the market of semiconductor devices of each type is estimated using a testing semiconductor device. Specifically, {circle around (1)} first, all types of semiconductor devices to be developed and mass-produced are classified into several groups. {circle around (2)} A test semiconductor device is developed which has the same number of elements, the same gate area, the same multi-layer wiring length and the same number of contact holes as the average number of elements, the average gate area, the average wiring length and the average number of contact holes of the semiconductor devices included in one of the type groups, respectively.
    Type: Grant
    Filed: March 11, 1999
    Date of Patent: April 24, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takehiro Hashimoto, Yutaka Tanaka, Tetsuya Asami, Youichi Satou, Noriaki Okumiya