Patents by Inventor Noriaki Shimada

Noriaki Shimada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210319528
    Abstract: A method includes: receiving space information regarding a target space of a cargo, the space information being divided into a plurality of sections and defining a route between the plurality of sections and a route from each of the plurality of sections to an entrance; generating, according to the space information, a first constraint condition indicating that there is no other cargo on a route from the cargo to be loaded or to be unloaded to the entrance during loading or unloading of the cargo, a second constraint condition indicating a number of cargos to be loaded and a number of cargos to be unloaded, and a third constraint condition indicating a maximum load capacity of each of the plurality of sections; and determining a cargo arrangement optimizing a degree of instability of the target space based on the first, second, and third constraint conditions.
    Type: Application
    Filed: March 22, 2021
    Publication date: October 14, 2021
    Applicant: FUJITSU LIMITED
    Inventors: Hideshi Yamaguchi, Noriaki Shimada
  • Patent number: 11106761
    Abstract: A computer-implemented optimization problem arithmetic method includes receiving a combinatorial optimization problem, determining, based on scale or a requested accuracy of the combinatorial optimization problem, a partition mode and an execution mode, the partition mode defining a logically divided state of an arithmetic circuit, the execution mode defining a range of hardware resources to be utilized in arithmetic operation for each of partitions generated by logically dividing the arithmetic circuit, and causing the arithmetic circuit to execute arithmetic operation of the combinatorial optimization problem in accordance with the determined partition mode and the determined execution mode.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: August 31, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Hiroshi Kondou, Hiroyuki Izui, Tatsuhiro Makino, Noriaki Shimada
  • Publication number: 20200089729
    Abstract: A computer-implemented optimization problem arithmetic method includes determining, based on management information indicating a partition mode that defines a logically divided state of each of a plurality of arithmetic circuits and utilization information relating to each of the plurality of arithmetic circuits, a partition mode of each of the plurality of arithmetic circuits, receiving a combinatorial optimization problem, selecting, based on information relating to scale or requested accuracy of the combinatorial optimization problem and the determined partition mode of each of the plurality of arithmetic units, a first arithmetic circuit from among the plurality of arithmetic circuits, and causing the selected first arithmetic circuit to execute arithmetic operation of the combinatorial optimization problem based on a first partition mode determined as the partition mode of the first arithmetic circuit.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 19, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Hiroshi Kondou, Hiroshi Yagi, Noriyuki Itakura, Noriaki Shimada
  • Publication number: 20200089475
    Abstract: A computer-implemented optimization problem arithmetic method includes receiving a combinatorial optimization problem, determining, based on scale or a requested accuracy of the combinatorial optimization problem, a partition mode and an execution mode, the partition mode defining a logically divided state of an arithmetic circuit, the execution mode defining a range of hardware resources to be utilized in arithmetic operation for each of partitions generated by logically dividing the arithmetic circuit, and causing the arithmetic circuit to execute arithmetic operation of the combinatorial optimization problem in accordance with the determined partition mode and the determined execution mode.
    Type: Application
    Filed: September 11, 2019
    Publication date: March 19, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Hiroshi Kondou, Hiroyuki Izui, Tatsuhiro Makino, Noriaki Shimada
  • Publication number: 20200089728
    Abstract: A computer-implemented optimization problem arithmetic method includes, receiving a combinatorial optimization problem, selecting a first arithmetic circuit from among a plurality of arithmetic circuits based on a scale or a requested accuracy of the combinatorial optimization problem and a partition mode that defines logically divided states of each of the plurality of arithmetic circuits, and causing the first arithmetic circuit to execute an arithmetic operation of the combinatorial optimization problem.
    Type: Application
    Filed: September 12, 2019
    Publication date: March 19, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Hiroshi Kondou, Hiroshi Yagi, Noriyuki Itakura, Noriaki Shimada
  • Publication number: 20200090051
    Abstract: An optimization problem operation method include accepting a combinatorial optimization problem to an operation unit that is capable of being divided into a plurality of partitions logically and solving the combinatorial optimization problem. The method include deciding a partition mode that prescribes a logical division state of the operation unit and an execution mode that prescribes a range of hardware resources used in an operation in the partition mode according to a scale or a requested precision of the combinatorial optimization problem. The method include causing execution of operations of the combinatorial optimization problem in parallel in the operation unit with the partition mode and the execution mode decided, based on the number of times obtained by dividing the number of times of execution of the combinatorial optimization problem by the number of divisions corresponding to the execution mode.
    Type: Application
    Filed: September 9, 2019
    Publication date: March 19, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Noriaki Shimada, Hiroyuki Izui, Hiroshi Kondou, Tatsuhiro Makino
  • Patent number: 9373930
    Abstract: A current Ii supplied to a pumping light source 20 is detected and time-averaged with a predetermined time constant to calculate a time-averaged current Iav. An optical output power Pi outputted from an amplifying optical fiber 12 is detected and time-averaged with the predetermined time constant to calculate a time-averaged optical output power Pav. A reference optical output power Pr and a reference current Ir supplied to the pumping light source 20 when the reference optical output power Pr is outputted from an optical fiber laser apparatus 1 are used to calculate an optical output power expectation value Pex=Iav×Pr/Ir. The time-averaged optical output power Pav and the optical output power expectation value Pex are compared with each other to determine a decrease of an optical output power of the optical amplifier apparatus 1 based on the comparison result.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: June 21, 2016
    Assignee: FUJIKURA LTD.
    Inventor: Noriaki Shimada
  • Publication number: 20160013612
    Abstract: A current Ii supplied to a pumping light source 20 is detected and time-averaged with a predetermined time constant to calculate a time-averaged current Iav. An optical output power Pi outputted from an amplifying optical fiber 12 is detected and time-averaged with the predetermined time constant to calculate a time-averaged optical output power Pav. A reference optical output power Pr and a reference current Ir supplied to the pumping light source 20 when the reference optical output power Pr is outputted from an optical fiber laser apparatus 1 are used to calculate an optical output power expectation value Pex=Iav×Pr/Ir. The time-averaged optical output power Pav and the optical output power expectation value Pex are compared with each other to determine a decrease of an optical output power of the optical amplifier apparatus 1 based on the comparison result.
    Type: Application
    Filed: September 22, 2015
    Publication date: January 14, 2016
    Applicant: FUJIKURA LTD.
    Inventor: Noriaki Shimada
  • Patent number: 6975446
    Abstract: An optical amplifier has a gain flatness which is maintained to be substantially constant regardless of temperature changes. The optical amplifier includes an EDF amplifying section and a Raman amplifying section, the Raman amplifying section having a temperature dependent gain profile which enables compensating for the temperature dependent gain profile of the EDF amplifying section. The Raman amplifying section includes a wavelength lock grating whose transmission wavelengths shift toward the short wavelength side as the temperature increases. The wavelength lock grating is preferably disposed to have the same temperature as that of an EDF of the EDF amplifying section. A method for compensating for temperature dependency of gain flatness of an optical amplifier and an optical transmission path including an optical amplifier are also disclosed.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: December 13, 2005
    Assignee: Fujikura Ltd.
    Inventors: Yasushi Takeda, Noriaki Shimada, Tetsuya Sakai, Akira Wada
  • Publication number: 20050130300
    Abstract: A method of culturing hepatocytes for a long term, characterized in that fresh hepatocytes are maintained in a medium at 15 to 30° C. for 1 to 6 days, followed by culturing under physiological conditions. The method of the present invention enables hepatocytes to be cultured for a long term without inviting reduction in enzymatic activity or enzyme-inducing activity. Moreover, since the cells can be maintained at around room temperature for 1 to 6 days, the method is very useful for long-term transportation of hepatocytes after isolation.
    Type: Application
    Filed: April 4, 2002
    Publication date: June 16, 2005
    Inventors: Noriaki Shimada, Patrick Maurel
  • Publication number: 20040042062
    Abstract: An optical amplifier has a gain flatness which is maintained to be substantially constant regardless of temperature changes. The optical amplifier includes an EDF amplifying section and a Raman amplifying section, the Raman amplifying section having a temperature dependent gain profile which enables compensating for the temperature dependent gain profile of the EDF amplifying section. The Raman amplifying section includes a wavelength lock grating whose transmission wavelengths shift toward the short wavelength side as the temperature increases. The wavelength lock grating is preferably disposed to have the same temperature as that of an EDF of the EDF amplifying section. A method for compensating for temperature dependency of gain flatness of an optical amplifier and an optical transmission path including an optical amplifier are also disclosed.
    Type: Application
    Filed: August 29, 2003
    Publication date: March 4, 2004
    Applicant: FUJIKURA LTD.
    Inventors: Yasushi Takeda, Noriaki Shimada, Tetsuya Sakai, Akira Wada