Abstract: A multi-function PC card includes: a first PC card interface that is capable to be coupled to a host device; a functional block that provides a first function to the host device; a second PC card interface that is capable to be coupled to an additional PC card; and an interface controller that allows one of the functional block and the additional PC card to be accessed by the host device through the first PC card interface.

Abstract: A multi-function PC card includes: a first PC card interface that is capable to be coupled to a host device; a functional block that provides a first function to the host device; a second PC card interface that is capable to be coupled to an additional PC card; and an interface controller that allows one of the functional block and the additional PC card to be accessed by the host device through the first PC card interface.

Abstract: A data transfer circuit includes a buffer, a counter and first and second collision circuits. The buffer stores write data in response to a write control signal and reads out data in response to a read control signal. The counter counts a number of data stored in the buffer and outputs a count value representing a number of the count. The first collision detection circuit is connected to the counter. The first collision detection circuit outputs the count value when the read control signal is in an inactive state and outputs a write prohibit signal when the read control signal is in an active state. The second collision detection circuit is connected to the counter. The second collision circuit outputs the count value when the write control signal is in an inactive state and outputs a read prohibit signal when the write control signal is in an active state.

Abstract: Data transfer control circuitry includes a receive buffer for sequentially receiving received data, which are provided from a local processor together with a write control signal to store the data therein, and sequentially developing the stored data in response to a read control signal, which is provided from a host in the same order as stored. A transmit buffer sequentially receives data to be transmitted, which are provided from the host together with another write control signal, and sequentially develops the stored data in response to another read control signal provided from the local processor in the same order as stored. A counter increments a count in response to a clock signal and resets itself in response to either of the write control signals. A clock control circuit interrupts the clock signal when the count reaches a preset value.

Abstract: A data transfer control circuit includes several data receiver-transmitters, each having an interrupt identification register. Interrupt signals from the data receiver-transmitters are combined into a single interrupt signal by an interrupt controller. One of the data receiver-transmitters has an interrupt status register with bits indicating the logic levels of the interrupt signals from each of the data receiver-transmitters. A host device that receives the interrupt signal from the interrupt controller can read the interrupt status register to determine which data receiver-transmitter caused the interrupt, then read the interrupt identification register of that data receiver-transmitter to identify the interrupt source, without having to search through the interrupt identification registers of other data receiver-transmitters.

Abstract: Data transfer control circuitry includes a receive buffer for sequentially receiving received data, which are provided from a local processor together with a write control signal to store the data therein, and sequentially developing the stored data in response to a read control signal, which is provided from a host in the same order as stored. A transmit buffer sequentially receives data to be transmitted, which are provided from the host together with another write control signal, and sequentially develops the stored data in response to another read control signal provided from the local processor in the same order as stored. A counter increments a count in response to a clock signal and resets itself in response to either of the write control signals. A clock control circuit interrupts the clock signal when the count reaches a preset value.

Abstract: Data transfer equipment enables high-speed transfer between a DTE (Data Terminal Equipment) and a DCE (Data Circuit Terminating Equipment). The data transfer equipment serves the DCE, and is connected through a first parallel bus to the DTE, and has a data processing section used to process data to be exchanged with the DTE. The data transfer equipment is provided with a transfer processing section connected to the data processing section through a second parallel bus, which is adapted to transfer, based on a specified control procedure, data received through the first parallel bus from the DTE to the data processing section through the second parallel bus and to transfer, based on the control procedures, data received through the second parallel bus from the data processing section to the DTE.

Abstract: Data transfer equipment is provided which enables high-speed transfer between a DTE (Data Terminal Equipment) and a DCE (Data Circuit Terminating Equipment).

Abstract: A data transfer control circuit includes several data receiver-transmitters, each having an interrupt identification register. Interrupt signals from the data receiver-transmitters are combined into a single interrupt signal by an interrupt controller. One of the data receiver-transmitters has an interrupt status register with bits indicating the logic levels of the interrupt signals from each of the data receiver-transmitters. A host device that receives the interrupt signal from the interrupt controller can read the interrupt status register to determine which data receiver-transmitter caused the interrupt, then read the interrupt identification register of that data receiver-transmitter to identify the interrupt source, without having to search through the interrupt identification registers of other data receiver-transmitters.

Abstract: In an integrated circuit combining a gate array with memory on a single semiconductor substrate, the interconnecting lines are routed in multiple metalization layers. In each layer having both memory and gate-array interconnecting lines, the memory interconnecting lines are routed over the memory area, and the gate-array interconnecting lines are routed in a different direction over the gate-array area. In layers having only gate-array interconnecting lines, some of these lines pass over the memory area, being routed directly above power-supply lines or shield lines provided in the layer just below.